stm32_eth: Multiple Improvements of the original codebase

stm32eth: Move to stm32_common periph cpu/stm32_periph_eth: Rebase to current master branch - Update DMA to use new vendor headers - Update send to use iolist. It looks like the packet headers are now transfered as seperate iolist entries which results in the eth periph sending each header as own packet. To fix this a rather ugly workaround is used where the whole iolist content is first copied to a static buffer. This will be fixed soon in another commit - If MAC is set to zero use luid to generate one - Small code style fixes cpu/stm312f7: Add periph config for on-board ethernet boards/nucleo-f767zi: Add config for on board ethernet tests/stm32_eth_lwip: Remove board restriction boards/common/nucleo: Add luid module if stm32 ethernet is used tests/stm32_eth_gnrc: Add Testcase for gnrc using the stm32 eth periph stm32_eth: Rework netdev driver layour tests/stm32_eth_*: Use netdev driver header file for prototypes stm32_eth: Add auto init for stm32 eth netdev driver boards/stm32: Enable ethernet conf for nucleo boards stm32_eth_auto_init: Add dont be pendantic flag stm32_eth: Remove dma specific stuff from periph_cpu.h Looks like this was implemented in PR #9171 and 021697a with the same interface. stm32_eth: Remove eth feature from stm32f4discovery boards stm32_eth: Migrate to stm32 DMA API stm32_eth: Add iolist to module deps stm32_eth: Rework send function to use iolist stm32_eth: Fix ci build warnings stm32_eth: Fix bug introduced with iolist usage stm32_eth: Remove redundant static buffer stm32_eth: Fix feature dependencies stm32_eth: Fix wrong header guard name stm32_eth: Implement correct l2 netstats interface stm32_eth: Rename public functions to stm32_eth_* stm32_eth: Fix doccheck stm32_eth: Move register DEFINE to appropriate header file stm32_eth: remove untested configuration for f446ze boards stm32_eth: Move periph configuration struct to stm32_common stm32_eth: Fix naming of eth_phy_read and eth_phy_write stm32_eth: Remove obsolete test applications
RIOT-OS · Jul 4, 2019 · 4729bea · 4729bea
1 parent e206087
commit 4729bea
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Showing 19 changed files with 517 additions and 657 deletions.
diff --git a/boards/nucleo-f767zi/Makefile.dep b/boards/nucleo-f767zi/Makefile.dep
@@ -1 +1,5 @@
+ifneq (,$(filter netdev_default gnrc_netdev_default,$(USEMODULE)))
+  USEMODULE += stm32_eth
+endif
+
 include $(RIOTBOARD)/common/nucleo/Makefile.dep
diff --git a/boards/nucleo-f767zi/Makefile.features b/boards/nucleo-f767zi/Makefile.features
@@ -6,6 +6,8 @@ FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_eth
+FEATURES_PROVIDED += periph_stm32_eth
 
 # load the common Makefile.features for Nucleo boards
 include $(RIOTBOARD)/common/nucleo144/Makefile.features

diff --git a/boards/nucleo-f767zi/include/periph_conf.h b/boards/nucleo-f767zi/include/periph_conf.h
@@ -40,11 +40,13 @@ static const dma_conf_t dma_config[] = {
     { .stream = 4 },    /* DMA1 Stream 4 - USART3_TX */
     { .stream = 14 },   /* DMA2 Stream 6 - USART6_TX */
     { .stream = 6 },    /* DMA1 Stream 6 - USART2_TX */
+    { .stream = 8 },    /* DMA2 Stream 8 - ETH_TX    */
 };
 
 #define DMA_0_ISR  isr_dma1_stream4
 #define DMA_1_ISR  isr_dma2_stream6
 #define DMA_2_ISR  isr_dma1_stream6
+#define DMA_3_ISR  isr_dma2_stream0
 
 #define DMA_NUMOF           (sizeof(dma_config) / sizeof(dma_config[0]))
 #endif
@@ -158,6 +160,41 @@ static const spi_conf_t spi_config[] = {
 #define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
 /** @} */
 
+
+/**
+ * @name ETH configuration
+ * @{
+ */
+#define ETH_NUMOF           (1)
+#define ETH_RX_BUFFER_COUNT (4)
+#define ETH_TX_BUFFER_COUNT (4)
+
+#define ETH_RX_BUFFER_SIZE (1524)
+#define ETH_TX_BUFFER_SIZE (1524)
+
+#define ETH_DMA_ISR        isr_dma2_stream0
+
+static const eth_conf_t eth_config = {
+    .mode = RMII,
+    .mac = { 0 },
+    .speed = ETH_SPEED_100TX_FD,
+    .dma_chan = 0,
+    .dma_stream = 8,
+    .phy_addr = 0x01,
+    .pins = {
+        GPIO_PIN(PORT_G, 13),
+        GPIO_PIN(PORT_B, 13),
+        GPIO_PIN(PORT_G, 11),
+        GPIO_PIN(PORT_C, 4),
+        GPIO_PIN(PORT_C, 5),
+        GPIO_PIN(PORT_A, 7),
+        GPIO_PIN(PORT_C, 1),
+        GPIO_PIN(PORT_A, 2),
+        GPIO_PIN(PORT_A, 1),
+    }
+};
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/boards/stm32f4discovery/Makefile.features b/boards/stm32f4discovery/Makefile.features
@@ -1,12 +1,10 @@
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_adc
 FEATURES_PROVIDED += periph_dac
-FEATURES_PROVIDED += periph_eth
 FEATURES_PROVIDED += periph_i2c
 FEATURES_PROVIDED += periph_pwm
 FEATURES_PROVIDED += periph_rtc
 FEATURES_PROVIDED += periph_spi
-FEATURES_PROVIDED += periph_stm32_eth
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 

diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h
@@ -211,41 +211,6 @@ static const i2c_conf_t i2c_config[] = {
 #define I2C_NUMOF           (sizeof(i2c_config) / sizeof(i2c_config[0]))
 /** @} */
 
-/**
- * @name ETH configuration
- * @{
- */
-#define ETH_NUMOF           (1)
-#define ETH_RX_BUFFER_COUNT (4)
-#define ETH_TX_BUFFER_COUNT (4)
-
-#define ETH_RX_BUFFER_SIZE (1524)
-#define ETH_TX_BUFFER_SIZE (1524)
-
-#define ETH_DMA_ISR        isr_dma2_stream0
-
-static const eth_conf_t eth_config = {
-    .mode = RMII,
-    .mac = { 1, 2, 3, 4, 5, 6 },
-    .speed = ETH_SPEED_100TX_FD,
-    .dma_chan = 0,
-    .dma_stream = 8,
-    .phy_addr = 0x01,
-    .pins = {
-        GPIO_PIN(PORT_B, 12),
-        GPIO_PIN(PORT_B, 13),
-        GPIO_PIN(PORT_B, 11),
-        GPIO_PIN(PORT_C, 4),
-        GPIO_PIN(PORT_C, 5),
-        GPIO_PIN(PORT_A, 7),
-        GPIO_PIN(PORT_C, 1),
-        GPIO_PIN(PORT_A, 2),
-        GPIO_PIN(PORT_A, 1),
-    }
-};
-
-/** @} */
-
 #ifdef __cplusplus
 }
 #endif

diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h
@@ -708,6 +708,168 @@ int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *
 #include "candev_stm32.h"
 #endif
 
+#ifdef MODULE_STM32_ETH
+
+/**
+ * @brief   Ethernet Peripheral configuration
+ */
+typedef struct {
+    enum {
+        MII = 18,                       /**< Configuration for MII */
+        RMII = 9,                       /**< Configuration for RMII */
+        SMI = 2,                        /**< Configuration for SMI */
+    } mode;                             /**< Select configuration mode */
+    enum {
+        ETH_SPEED_10T_HD = 0x0000,
+        ETH_SPEED_10T_FD = 0x0100,
+        ETH_SPEED_100TX_HD = 0x2000,
+        ETH_SPEED_100TX_FD = 0x2100,
+    } speed;                            /**< Speed selection */
+    uint8_t dma;                        /**< Locical CMA Descriptor used for TX */
+    uint8_t dma_chan;                   /**< DMA channel used for TX */
+    char mac[6];                        /**< Et hernet MAC address */
+    char phy_addr;                      /**< PHY address */
+    gpio_t pins[];                      /**< Pins to use. MII requires 18 pins,
+                                             RMII 9 and SMI 9. Not all speeds are
+                                             supported by all modes. */
+} eth_conf_t;
+
+/**
+* @name Ethernet PHY Common Registers
+* @{
+*/
+#define PHY_BMCR                           (0x00)
+#define PHY_BSMR                           (0x01)
+#define PHY_PHYIDR1                        (0x02)
+#define PHY_PHYIDR2                        (0x03)
+#define PHY_ANAR                           (0x04)
+#define PHY_ANLPAR                         (0x05)
+#define PHY_ANER                           (0x06)
+#define PHY_ANNPTR                         (0x07)
+/** @} */
+
+/**
+* @name Ethernet PHY BMCR Fields
+* @{
+*/
+#define BMCR_RESET                         (0x8000)
+#define BMCR_LOOPBACK                      (0x4000)
+#define BMCR_SPEED_SELECT                  (0x2000)
+#define BMCR_AN                            (0x1000)
+#define BMCR_POWER_DOWN                    (0x0800)
+#define BMCR_ISOLATE                       (0x0400)
+#define BMCR_RESTART_AN                    (0x0200)
+#define BMCR_DUPLEX_MODE                   (0x0100)
+#define BMCR_COLLISION_TEST                (0x0080)
+/** @} */
+
+/**
+* @name Ethernet PHY BSMR Fields
+* @{
+*/
+#define BSMR_100BASE_T4                    (0x8000)
+#define BSMR_100BASE_TX_FDUPLEX            (0x4000)
+#define BSMR_100BASE_TX_HDUPLEX            (0x2000)
+#define BSMR_10BASE_T_FDUPLEX              (0x1000)
+#define BSMR_10BASE_T_HDUPLEX              (0x0800)
+#define BSMR_NO_PREAMBLE                   (0x0040)
+#define BSMR_AN_COMPLETE                   (0x0020)
+#define BSMR_REMOTE_FAULT                  (0x0010)
+#define BSMR_AN_ABILITY                    (0x0008)
+#define BSMR_LINK_STATUS                   (0x0004)
+#define BSMR_JABBER_DETECT                 (0x0002)
+#define BSMR_EXTENDED_CAP                  (0x0001)
+/** @} */
+
+/**
+* @name Ethernet PHY PHYIDR1 Fields
+*/
+#define PHYIDR1_OUI                        (0xffff)
+
+/**
+* @name Ethernet PHY PHYIDR2 Fields
+* @{
+*/
+#define PHYIDR2_OUI                        (0xfe00)
+#define PHYIDR2_MODEL                      (0x01f0)
+#define PHYIDR2_REV                        (0x0007)
+/** @} */
+
+/**
+* @name Ethernet PHY ANAR Fields
+* @{
+*/
+#define ANAR_NEXT_PAGE                     (0x8000)
+#define ANAR_REMOTE_FAULT                  (0x2000)
+#define ANAR_PAUSE                         (0x0600)
+#define ANAR_100BASE_T4                    (0x0200)
+#define ANAR_100BASE_TX_FDUPLEX            (0x0100)
+#define ANAR_100BASE_TX_HDUPLEX            (0x0080)
+#define ANAR_10BASE_T_FDUPLEX              (0x0040)
+#define ANAR_10BASE_T_HDUPLEX              (0x0020)
+#define ANAR_SELECTOR                      (0x000f)
+/** @} */
+
+/**
+* @name Ethernet PHY ANLPAR Fields
+* @{
+*/
+#define ANLPAR_NEXT_PAGE                   (0x8000)
+#define ANLPAR_ACK                         (0x4000)
+#define ANLPAR_REMOTE_FAULT                (0x2000)
+#define ANLPAR_PAUSE                       (0x0600)
+#define ANLPAR_100BASE_T4                  (0x0200)
+#define ANLPAR_100BASE_TX_FDUPLEX          (0x0100)
+#define ANLPAR_100BASE_TX_HDUPLEX          (0x0080)
+#define ANLPAR_10BASE_T_FDUPLEX            (0x0040)
+#define ANLPAR_10BASE_T_HDUPLEX            (0x0020)
+#define ANLPAR_SELECTOR                    (0x000f)
+/** @} */
+
+/**
+* @name Ethernet PHY ANNPTR Fields
+* @{
+*/
+#define ANNPTR_NEXT_PAGE                   (0x8000)
+#define ANNPTR_MSG_PAGE                    (0x2000)
+#define ANNPTR_ACK2                        (0x1000)
+#define ANNPTR_TOGGLE_TX                   (0x0800)
+#define ANNPTR_CODE                        (0x03ff)
+/** @} */
+
+/**
+* @name Ethernet PHY ANER Fields
+* @{
+*/
+#define ANER_PDF                           (0x0010)
+#define ANER_LP_NEXT_PAGE_ABLE             (0x0008)
+#define ANER_NEXT_PAGE_ABLE                (0x0004)
+#define ANER_PAGE_RX                       (0x0002)
+#define ANER_LP_AN_ABLE                    (0x0001)
+/** @} */
+
+/**
+ * @brief Read a PHY register
+ *
+ * @param[in] addr      address of the PHY to read
+ * @param[in] reg       register to be read
+ *
+ * @return value in the register, or <=0 on error
+ */
+int32_t stm32_eth_phy_read(uint16_t addr, uint8_t reg);
+
+/**
+ * @brief Write a PHY register
+ *
+ * @param[in] addr      address of the PHY to write
+ * @param[in] reg       register to be written
+ * @param[in] value     value to write into the register
+ *
+ * @return 0 in case of success or <=0 on error
+ */
+int32_t stm32_eth_phy_write(uint16_t addr, uint8_t reg, uint16_t value);
+#endif /* MODULE_STM32_ETH */
+
 #ifdef __cplusplus
 }
 #endif