boards/nucleo-f401: adapted to UART driver update

RIOT-OS · Dec 7, 2015 · 84fd4d7 · 84fd4d7
1 parent b75e5fe
commit 84fd4d7
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Showing 2 changed files with 27 additions and 18 deletions.
diff --git a/boards/nucleo-f401/include/board.h b/boards/nucleo-f401/include/board.h
@@ -47,7 +47,7 @@ extern "C" {
  * @name Define UART device and baudrate for stdio
  * @{
  */
-#define STDIO               UART_0
+#define STDIO               UART_DEV(0)
 #define STDIO_BAUDRATE      (115200U)
 #define STDIO_RX_BUFSIZE    (64U)
 /** @} */

diff --git a/boards/nucleo-f401/include/periph_conf.h b/boards/nucleo-f401/include/periph_conf.h
@@ -19,6 +19,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -39,6 +41,11 @@ extern "C" {
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
@@ -73,24 +80,26 @@ extern "C" {
  * @name UART configuration
  * @{
  */
-#define UART_NUMOF          (1U)
-#define UART_0_EN           1
-#define UART_IRQ_PRIO       1
-#define UART_CLK            (14000000U)         /* UART clock runs with 14MHz */
-
-/* UART 0 device configuration */
-#define UART_0_DEV          USART2
-#define UART_0_CLKEN()      (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
-#define UART_0_CLKDIS()     (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define UART_0_CLK          (CLOCK_CORECLOCK / 2)          /* UART clock runs with 42MHz (F_CPU / 2) */
-#define UART_0_IRQ_CHAN     USART2_IRQn
+static const uart_conf_t uart_config[] = {
+    /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA  */
+    {
+        USART2,                     /* device base register */
+        RCC_APB1ENR_USART2EN,       /* RCC mask */
+        GPIO_PIN(PORT_A,3),         /* RX pin */
+        GPIO_PIN(PORT_A,2),         /* TX pin */
+        GPIO_AF7,                   /* pin AF */
+        USART2_IRQn,                /* IRQ channel */
+        6,                          /* DMA stream */
+        4                           /* DMA channel */
+    }
+};
+
+/* assign ISR vector names */
 #define UART_0_ISR          isr_usart2
-/* UART 0 pin configuration */
-#define UART_0_PORT         GPIOA
-#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
-#define UART_0_RX_PIN       3
-#define UART_0_TX_PIN       2
-#define UART_0_AF           7
+#define UART_0_DMA_ISR      isr_dma1_stream6
+
+/* deduct number of defined UART interfaces */
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
 /** @} */
 
 /**