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cpu/stm32wl: Enable rtc support #20536

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cpu/stm32wl: Enable rtc support #20536

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1 change: 1 addition & 0 deletions boards/nucleo-wl55jc/Makefile.features
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@ CPU_MODEL = stm32wl55jc
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_lpuart
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
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16 changes: 8 additions & 8 deletions cpu/stm32/periph/rtc_all.c
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->PR1)
#define EXTI_REG_IMR (EXTI->IMR1)
#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5)
#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL)
#define EXTI_REG_RTSR (EXTI->RTSR1)
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->RPR1)
Expand All @@ -73,7 +73,7 @@
#define RTC_ISR_INITF RTC_ICSR_INITF
#define RTC_ISR_ALRAWF RTC_ICSR_ALRAWF
#define RTC_ISR_ALRAF RTC_SR_ALRAF
#elif defined(CPU_FAM_STM32L5)
#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define RTC_REG_ISR RTC->ICSR
#define RTC_REG_SR RTC->SR
#define RTC_REG_SCR RTC->SCR
Expand Down Expand Up @@ -111,7 +111,7 @@
#define EXTI_FTSR_BIT (EXTI_FTSR1_FT18)
#define EXTI_RTSR_BIT (EXTI_RTSR1_RT18)
#define EXTI_PR_BIT (EXTI_PR1_PIF18)
#elif defined(CPU_FAM_STM32L5)
#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
#define EXTI_IMR_BIT (EXTI_IMR1_IM17)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#define EXTI_IMR_BIT (EXTI_IMR1_IM17)
Expand Down Expand Up @@ -274,7 +274,7 @@

/* select input clock and enable the RTC */
stmclk_dbp_unlock();
#if defined(CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
periph_clk_en(APB1, RCC_APB1ENR1_RTCAPBEN);
#elif defined(CPU_FAM_STM32G0)
periph_clk_en(APB1, RCC_APBENR1_RTCAPBEN);
Expand All @@ -299,7 +299,7 @@
/* configure the EXTI channel, as RTC interrupts are routed through it.
* Needs to be configured to trigger on rising edges. */
EXTI_REG_IMR |= EXTI_IMR_BIT;
#if !defined(CPU_FAM_STM32L5)
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL))
EXTI_REG_FTSR &= ~(EXTI_FTSR_BIT);
EXTI_REG_RTSR |= EXTI_RTSR_BIT;
EXTI_REG_PR = EXTI_PR_BIT;
Expand Down Expand Up @@ -363,7 +363,7 @@
val2bcd(time->tm_sec, RTC_ALRMAR_SU_Pos, ALRM_S_MASK));

/* Enable Alarm A */
#if !defined(CPU_FAM_STM32L5)
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL))
RTC_REG_ISR &= ~(RTC_ISR_ALRAF);
#else
RTC_REG_SCR = RTC_SCR_CALRAF;
Expand Down Expand Up @@ -396,7 +396,7 @@

RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);

#if !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32U5)
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32WL))
while (!(RTC_REG_ISR & RTC_ISR_ALRAWF)) {}
#else
RTC_REG_SCR = RTC_SCR_CALRAF;
Expand Down Expand Up @@ -424,7 +424,7 @@

void ISR_NAME(void)
{
#if !defined(CPU_FAM_STM32L5) && !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32U5)
#if !(defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32U5))

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if (RTC_REG_ISR & RTC_ISR_ALRAF) {
if (isr_ctx.cb != NULL) {
isr_ctx.cb(isr_ctx.arg);
Expand Down