Windows fix

RPCS3 · Jan 22, 2024 · 96b369c · 96b369c
1 parent 83107e1
commit 96b369c
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp
@@ -689,8 +689,10 @@ bool FSMB(spu_thread& spu, spu_opcode_t op)
 template <spu_exec_bit... Flags>
 bool FREST(spu_thread& spu, spu_opcode_t op)
 {
-	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18) & _mm_set1_epi32(0x1F);
-	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23) & _mm_set1_epi32(0xFF);
+	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18);
+	fraction_index &= _mm_set1_epi32(0x1F);
+	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23);
+	exponent_index &= _mm_set1_epi32(0xFF);
 	v128 sign = spu.gpr[op.ra] & _mm_set1_epi32(0x80000000);
 
 	// AVX2
@@ -714,8 +716,10 @@ bool FREST(spu_thread& spu, spu_opcode_t op)
 template <spu_exec_bit... Flags>
 bool FRSQEST(spu_thread& spu, spu_opcode_t op)
 {
-	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18) & _mm_set1_epi32(0x3F);
-	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23) & _mm_set1_epi32(0xFF);
+	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18);
+	fraction_index &= _mm_set1_epi32(0x3F);
+	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23);
+	exponent_index &= _mm_set1_epi32(0xFF);
 
 	// AVX2
 	// v128 fraction = _mm_i32gather_epi32(spu_frsqest_fraction_lut, fraction_index, 4);