Fix

RPCS3 · Jan 22, 2024 · df6c8f7 · df6c8f7
1 parent 83107e1
commit df6c8f7
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp
@@ -689,8 +689,8 @@ bool FSMB(spu_thread& spu, spu_opcode_t op)
 template <spu_exec_bit... Flags>
 bool FREST(spu_thread& spu, spu_opcode_t op)
 {
-	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18) & _mm_set1_epi32(0x1F);
-	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23) & _mm_set1_epi32(0xFF);
+	v128 fraction_index = v128(_mm_srli_epi32(spu.gpr[op.ra], 18)) & v128(_mm_set1_epi32(0x1F));
+	v128 exponent_index = v128(_mm_srli_epi32(spu.gpr[op.ra], 23)) & v128(_mm_set1_epi32(0xFF));
 	v128 sign = spu.gpr[op.ra] & _mm_set1_epi32(0x80000000);
 
 	// AVX2
@@ -714,8 +714,8 @@ bool FREST(spu_thread& spu, spu_opcode_t op)
 template <spu_exec_bit... Flags>
 bool FRSQEST(spu_thread& spu, spu_opcode_t op)
 {
-	v128 fraction_index = _mm_srli_epi32(spu.gpr[op.ra], 18) & _mm_set1_epi32(0x3F);
-	v128 exponent_index = _mm_srli_epi32(spu.gpr[op.ra], 23) & _mm_set1_epi32(0xFF);
+	v128 fraction_index = v128(_mm_srli_epi32(spu.gpr[op.ra], 18)) & v128(_mm_set1_epi32(0x3F));
+	v128 exponent_index = v128(_mm_srli_epi32(spu.gpr[op.ra], 23)) & v128(_mm_set1_epi32(0xFF));
 
 	// AVX2
 	// v128 fraction = _mm_i32gather_epi32(spu_frsqest_fraction_lut, fraction_index, 4);