Minor UB fix

RPCS3 · Oct 10, 2019 · f754fb1 · f754fb1
1 parent eee0dfb
commit f754fb1
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Showing 6 changed files with 11 additions and 11 deletions.
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.cpp b/rpcs3/Emu/Cell/PPUInterpreter.cpp
@@ -3935,7 +3935,7 @@ bool ppu_interpreter::DIVW(ppu_thread& ppu, ppu_opcode_t op)
 {
 	const s32 RA = (s32)ppu.gpr[op.ra];
 	const s32 RB = (s32)ppu.gpr[op.rb];
-	const bool o = RB == 0 || ((u32)RA == (1 << 31) && RB == -1);
+	const bool o = RB == 0 || (RA == (-1 << 31) && RB == -1);
 	ppu.gpr[op.rd] = o ? 0 : u32(RA / RB);
 	if (UNLIKELY(op.oe)) ppu_ov_set(ppu, o);
 	if (UNLIKELY(op.rc)) ppu_cr_set(ppu, 0, false, false, false, ppu.xer.so);

diff --git a/rpcs3/Emu/Cell/PPUTranslator.cpp b/rpcs3/Emu/Cell/PPUTranslator.cpp
@@ -2996,8 +2996,8 @@ void PPUTranslator::DIVW(ppu_opcode_t op)
 {
 	const auto a = GetGpr(op.ra, 32);
 	const auto b = GetGpr(op.rb, 32);
-	const auto o = m_ir->CreateOr(IsZero(b), m_ir->CreateAnd(m_ir->CreateICmpEQ(a, m_ir->getInt32(1 << 31)), IsOnes(b)));
-	const auto result = m_ir->CreateSDiv(a, m_ir->CreateSelect(o, m_ir->getInt32(1 << 31), b));
+	const auto o = m_ir->CreateOr(IsZero(b), m_ir->CreateAnd(m_ir->CreateICmpEQ(a, m_ir->getInt32(1u << 31)), IsOnes(b)));
+	const auto result = m_ir->CreateSDiv(a, m_ir->CreateSelect(o, m_ir->getInt32(1u << 31), b));
 	SetGpr(op.rd, m_ir->CreateSelect(o, m_ir->getInt32(0), result));
 	if (op.rc) SetCrField(0, GetUndef<bool>(), GetUndef<bool>(), GetUndef<bool>());
 	if (op.oe) SetOverflow(o);

diff --git a/rpcs3/Emu/Cell/lv2/sys_lwmutex.cpp b/rpcs3/Emu/Cell/lv2/sys_lwmutex.cpp
@@ -96,7 +96,7 @@ error_code _sys_lwmutex_lock(ppu_thread& ppu, u32 lwmutex_id, u64 timeout)
 
 		if (old)
 		{
-			if (old == (1 << 31))
+			if (old == (-1 << 31))
 			{
 				ppu.gpr[3] = CELL_EBUSY;
 			}
@@ -230,7 +230,7 @@ error_code _sys_lwmutex_unlock2(ppu_thread& ppu, u32 lwmutex_id)
 			return;
 		}
 
-		mutex.signaled |= 1 << 31;
+		mutex.signaled |= -1 << 31;
 	});
 
 	if (!mutex)

diff --git a/rpcs3/Emu/RSX/RSXThread.cpp b/rpcs3/Emu/RSX/RSXThread.cpp
@@ -2028,7 +2028,7 @@ namespace rsx
 		const s32 default_frequency_mask = (1 << 8);
 		const s32 swap_storage_mask = (1 << 29);
 		const s32 volatile_storage_mask = (1 << 30);
-		const s32 modulo_op_frequency_mask = (1 << 31);
+		const s32 modulo_op_frequency_mask = (-1 << 31);
 
 		const u32 modulo_mask = rsx::method_registers.frequency_divider_operation_mask();
 		const auto max_index = (first_vertex + vertex_count) - 1;

diff --git a/rpcs3/Emu/RSX/gcm_enums.h b/rpcs3/Emu/RSX/gcm_enums.h
@@ -575,7 +575,7 @@ enum
 	CELL_GCM_TEXTURE_CYLINDRICAL_WRAP_ENABLE_TEX7_U = 1 << 28,
 	CELL_GCM_TEXTURE_CYLINDRICAL_WRAP_ENABLE_TEX7_V = 1 << 29,
 	CELL_GCM_TEXTURE_CYLINDRICAL_WRAP_ENABLE_TEX7_P = 1 << 30,
-	CELL_GCM_TEXTURE_CYLINDRICAL_WRAP_ENABLE_TEX7_Q = 1 << 31,
+	CELL_GCM_TEXTURE_CYLINDRICAL_WRAP_ENABLE_TEX7_Q = -1 << 31,
 
 	CELL_GCM_COLOR_MASK_B = 1 << 0,
 	CELL_GCM_COLOR_MASK_G = 1 << 8,

diff --git a/rpcs3/Emu/RSX/rsx_decode.h b/rpcs3/Emu/RSX/rsx_decode.h
@@ -2027,14 +2027,14 @@ struct registers_decoder<NV3089_DS_DX>
 		{
 			const u32 val = value;
 
-			if ((val & ~(1<<31)) == 0)
+			if ((val & ~(-1<<31)) == 0)
 			{
 				return 0;
 			}
 
 			if ((s32)val < 0)
 			{
-				return 1.f / (((val & ~(1<<31)) / 1048576.f) - 2048.f);
+				return 1.f / (((val & ~(-1<<31)) / 1048576.f) - 2048.f);
 			}
 
 			return 1048576.f / val;
@@ -2063,14 +2063,14 @@ struct registers_decoder<NV3089_DT_DY>
 		{
 		    const u32 val = value;
 
-			if ((val & ~(1<<31)) == 0)
+			if ((val & ~(-1<<31)) == 0)
 			{
 				return 0;
 			}
 
 			if ((s32)val < 0)
 			{
-				return 1.f / (((val & ~(1<<31)) / 1048576.f) - 2048.f);
+				return 1.f / (((val & ~(-1<<31)) / 1048576.f) - 2048.f);
 			}
 
 			return 1048576.f / val;