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SPU LLVM: Handle SHUFB special cases with a lookup table #11257

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merged 2 commits into from
Jul 18, 2023

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Whatcookie
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Use a lookup table to handle the special cases for the SHUFB instruction.

Needs 3 instructions to handle the special cases, vs the 5 instructions of the previous implementation. We need 3 instructions since x86 lacks an 8 bit simd shift instruction (could be just 2 otherwise).

@Megamouse Megamouse added CPU Optimization Optimizes existing code labels Dec 15, 2021
@Nekotekina
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I often see that AVG phase is eliminated completely in many cases because it's transparent for the optimizer to figure out that certain bits are never set. PSHUFB is not so transparent, however. May need to replay KnownBits analysis on IR generation stage which I planned for a while.

@AniLeo AniLeo requested a review from Nekotekina June 11, 2022 06:00
@elad335
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elad335 commented Jul 17, 2023

cpu_translator::get_known_bits is implemented now, needs updating.

- Needs 3 instructions to handle the special cases, since x86 lacks an 8 bit simd shift instruction
@elad335 elad335 force-pushed the spu branch 4 times, most recently from 40948ea to 0768c6b Compare July 18, 2023 18:59
@elad335 elad335 merged commit 50dad68 into RPCS3:master Jul 18, 2023
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4 participants