SPU LLVM: Optimize GB/GBH/GBB with a GFNI path #14669
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- Abuses GFNI to extract bits from bytes, from 5->2 instructions in most cases
Megamouse
added
CPU
Optimization
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It also needs to load the constant into xmm1 right? it's not 2 instructions unless Im missing something. |
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2 instructions discounting constants, gbb needs 3 instructions |
Nekotekina
reviewed
Sep 23, 2023
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By treating the first input as constant, and the second input as variable, with only 1 bit set in our constant, gf2p8affineqb will extract that selected bit from each byte of the second operand.
Brings the needed instructions down to just 2, from the worst case of 6 (GBH), and avoids round trips between vector->int->vector registers
CPUs that can take this path are 11th gen and onward for Intel, and zen4 (Ryzen 7000) and onward for AMD.
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