PPU interpreters: Implement AltiVec (vector) NaN precedence and data preservation #8218
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VelocityRa
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VelocityRa
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Testcase : https://github.com/elad335/myps3tests/tree/master/ppu_tests/AltiVec%20NaN%20precedence |
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Any review? |
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If any of the operands is a NaN of any kind it is 'quited' (MSB of fraction is set) and returned with the following ordering of selection between the NaNs: VA, VB, VC, result of operation.
The resulted NaN of operation is returned as a NaN if none of the arguments is a NaN.
Sign and fraction bits (other than NaN's signaling bit) are preserved across operands in all instructions.
It's not implemented at PPU LLVM atm.