Implemented Control Unit, Datapath, ALU, Registers, Finite State Machine, and other components in System Verilog. Included basic operations such as add, subtract, XOR, bitwise OR, and bitwise AND. Collaborated with a colleague at the University of Washington Tacoma to design and implement this project.
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Implemented Control Unit, Datapath, ALU, Registers, Finite State Machine, and other components in System Verilog. Included basic operations such as add, subtract, XOR, bitwise OR, and bitwise AND.
RohanSeam/Six-Instruction-Processor
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Implemented Control Unit, Datapath, ALU, Registers, Finite State Machine, and other components in System Verilog. Included basic operations such as add, subtract, XOR, bitwise OR, and bitwise AND.
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