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Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and …
…CLZ thumb instructions (#3683) * Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg) * Bump PPTC version
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,16 @@ | ||
namespace ARMeilleure.Decoders | ||
{ | ||
class OpCodeT32AluImm12 : OpCodeT32Alu, IOpCode32AluImm | ||
{ | ||
public int Immediate { get; } | ||
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public bool IsRotated => false; | ||
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluImm12(inst, address, opCode); | ||
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public OpCodeT32AluImm12(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) | ||
{ | ||
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800); | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,14 @@ | ||
namespace ARMeilleure.Decoders | ||
{ | ||
class OpCodeT32AluReg : OpCodeT32Alu, IOpCode32AluReg | ||
{ | ||
public int Rm { get; } | ||
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluReg(inst, address, opCode); | ||
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public OpCodeT32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) | ||
{ | ||
Rm = (opCode >> 0) & 0xf; | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,19 @@ | ||
using ARMeilleure.Common; | ||
using System.Runtime.Intrinsics; | ||
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namespace ARMeilleure.Decoders | ||
{ | ||
class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm | ||
{ | ||
public int Immediate { get; } | ||
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public bool IsRotated => false; | ||
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode); | ||
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public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) | ||
{ | ||
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000); | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,19 @@ | ||
namespace ARMeilleure.Decoders | ||
{ | ||
class OpCodeT32ShiftReg : OpCodeT32Alu, IOpCode32AluRsReg | ||
{ | ||
public int Rm => Rn; | ||
public int Rs { get; } | ||
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public ShiftType ShiftType { get; } | ||
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32ShiftReg(inst, address, opCode); | ||
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public OpCodeT32ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) | ||
{ | ||
Rs = (opCode >> 0) & 0xf; | ||
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ShiftType = (ShiftType)((opCode >> 21) & 3); | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,16 @@ | ||
namespace ARMeilleure.Decoders | ||
{ | ||
class OpCodeT32Tb : OpCodeT32, IOpCode32BReg | ||
{ | ||
public int Rm { get; } | ||
public int Rn { get; } | ||
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32Tb(inst, address, opCode); | ||
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public OpCodeT32Tb(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) | ||
{ | ||
Rm = (opCode >> 0) & 0xf; | ||
Rn = (opCode >> 16) & 0xf; | ||
} | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -545,6 +545,8 @@ enum InstName | |
Strexh, | ||
Strh, | ||
Sxtb16, | ||
Tbb, | ||
Tbh, | ||
Teq, | ||
Trap, | ||
Tst, | ||
|
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