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LINUX-STM32MP: v5.15-stm32mp-r2.1
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Change-Id: Icc53eff4868b9b5819af646224d1620c2dc514fa
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
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RJESTM committed Aug 3, 2023
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10 changes: 5 additions & 5 deletions ...15.67/0001-v5.15-stm32mp-r2-MACHINE.patch → ...118/0001-v5.15-stm32mp-r2.1-MACHINE.patch
View file
@@ -1,9 +1,9 @@
From 84827f5873b8cd852cc79177e9a42b12760b3723 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 13 Oct 2022 12:22:34 +0200
Subject: [PATCH 01/22] v5.15-stm32mp-r2 MACHINE
From 79ae410c50b3664a3006547c2235128e5f4736d1 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:34:11 +0200
Subject: [PATCH 01/22] v5.15-stm32mp-r2.1 MACHINE

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
Documentation/arm/index.rst | 1 +
.../arm/stm32/stm32mp13-overview.rst | 37 +++++++++++++++++++
Expand Down
12 changes: 6 additions & 6 deletions ...5.15.67/0002-v5.15-stm32mp-r2-CLOCK.patch → ...5.118/0002-v5.15-stm32mp-r2.1-CLOCK.patch
View file
@@ -1,9 +1,9 @@
From 7fce50075a5475b4af7b4918076e0577457530c9 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:22:35 +0100
Subject: [PATCH 02/22] v5.15-stm32mp-r2 CLOCK
From b931df769e83687f9676f7fbe0154b9a88c3812e Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:35:04 +0200
Subject: [PATCH 02/22] v5.15-stm32mp-r2.1 CLOCK

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
drivers/clk/Kconfig | 5 +
drivers/clk/Makefile | 1 +
Expand Down Expand Up @@ -32,7 +32,7 @@ Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c5b3dc97396a..c23287f7d108 100644
index 100e474ff3dc..0a93f074cede 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -334,6 +334,11 @@ config COMMON_CLK_VC5
Expand Down
93 changes: 12 additions & 81 deletions ...15.67/0003-v5.15-stm32mp-r2-CPUFREQ.patch → ...118/0003-v5.15-stm32mp-r2.1-CPUFREQ.patch
View file
@@ -1,86 +1,17 @@
From 7b129c9db71e9dcb515a4585861898b6a3644f1b Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:23:32 +0100
Subject: [PATCH 03/22] v5.15-stm32mp-r2 CPUFREQ
From 3297b2b5cfda8baab37e49aadea8b6fc6a755326 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:35:55 +0200
Subject: [PATCH 03/22] v5.15-stm32mp-r2.1 CPUFREQ

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
.../bindings/cpufreq/stm32-cpufreq.txt | 61 +++++++++++
drivers/cpufreq/Kconfig.arm | 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/stm32-cpufreq.c | 103 ++++++++++++++++++
5 files changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
drivers/cpufreq/Kconfig.arm | 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/stm32-cpufreq.c | 103 +++++++++++++++++++++++++++
4 files changed, 112 insertions(+)
create mode 100644 drivers/cpufreq/stm32-cpufreq.c

diff --git a/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
new file mode 100644
index 000000000000..1292eb2612a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/stm32-cpufreq.txt
@@ -0,0 +1,61 @@
+STM32 CPUFreq and OPP bindings
+==============================
+
+STM32 CPUFreq driver needs to read chip information from the SoC to list
+available OPPs. Then it depends on cpufreq-dt bindings.
+
+Required properties:
+--------------------
+- clocks: Phandle to the cpu clock "cpu".
+- clocks-name: Should contain "cpu".
+- nvmem-cells: Phandle to nvmem cell that contains "part_number".
+- nvmem-cell-names: Must be "part_number".
+- operating-points-v2: Phandle to operating points table. See ../power/opp.txt
+ for more details.
+
+Optional properties:
+--------------------
+See cpufreq-dt.txt for optional properties.
+
+Examples:
+---------
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ nvmem-cells = <&part_number_otp>;
+ nvmem-cell-names = "part_number";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&rcc CK_MPU>;
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0x1>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1350000>;
+ opp-supported-hw = <0x2>;
+ };
+ };
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 954749afb5fe..eac08e90768c 100644
--- a/drivers/cpufreq/Kconfig.arm
Expand Down Expand Up @@ -112,10 +43,10 @@ index 48ee5859030c..d34de1b927bf 100644
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ca1d103ec449..f205e6e9703e 100644
index e1b5975c7daa..9e3cd2746eeb 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -150,6 +150,7 @@ static const struct of_device_id blocklist[] __initconst = {
@@ -152,6 +152,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "st,stih407", },
{ .compatible = "st,stih410", },
{ .compatible = "st,stih418", },
Expand Down
10 changes: 5 additions & 5 deletions ...0004-v5.15-stm32mp-r2-CPUIDLE-POWER.patch → ...04-v5.15-stm32mp-r2.1-CPUIDLE-POWER.patch
View file
@@ -1,9 +1,9 @@
From dc62943bb269dbe5f3294beda26e299bb00f0e97 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 16:49:53 +0100
Subject: [PATCH 04/22] v5.15-stm32mp-r2 CPUIDLE-POWER
From 06dab8c8240a3a813f147ce5daa94b64eaf9ff9f Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:37:00 +0200
Subject: [PATCH 04/22] v5.15-stm32mp-r2.1 CPUIDLE-POWER

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
drivers/cpuidle/Kconfig.arm | 8 +
drivers/cpuidle/Makefile | 1 +
Expand Down
50 changes: 8 additions & 42 deletions ....15.67/0005-v5.15-stm32mp-r2-CRYPTO.patch → ....118/0005-v5.15-stm32mp-r2.1-CRYPTO.patch
View file
@@ -1,48 +1,14 @@
From 0d2fcaf7ef322a9caec811097a3877d9a89eaae4 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:26:07 +0100
Subject: [PATCH 05/22] v5.15-stm32mp-r2 CRYPTO
From 313fd2a08ceee58571f3af89fbb740710cb9db42 Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:37:32 +0200
Subject: [PATCH 05/22] v5.15-stm32mp-r2.1 CRYPTO

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
.../bindings/crypto/st,stm32-cryp.yaml | 9 +
.../bindings/crypto/st,stm32-hash.yaml | 1 +
drivers/crypto/stm32/stm32-cryp.c | 741 ++++++++++++-
drivers/crypto/stm32/stm32-hash.c | 999 ++++++++++++------
4 files changed, 1409 insertions(+), 341 deletions(-)
drivers/crypto/stm32/stm32-cryp.c | 741 ++++++++++++++++++++--
drivers/crypto/stm32/stm32-hash.c | 999 +++++++++++++++++++++---------
2 files changed, 1399 insertions(+), 341 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
index a4574552502a..6c3f8f7bfd67 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
@@ -27,6 +27,15 @@ properties:
resets:
maxItems: 1

+ dmas:
+ maxItems: 2
+ minItems: 2
+
+ dma-names:
+ items:
+ - const: in
+ - const: out
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 6dd658f0912c..1a944608d8ff 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- st,stm32f456-hash
- st,stm32f756-hash
+ - st,stm32mp13-hash

reg:
maxItems: 1
diff --git a/drivers/crypto/stm32/stm32-cryp.c b/drivers/crypto/stm32/stm32-cryp.c
index 81eb136b6c11..d76641596db4 100644
--- a/drivers/crypto/stm32/stm32-cryp.c
Expand Down
136 changes: 9 additions & 127 deletions ...5/5.15.67/0006-v5.15-stm32mp-r2-DMA.patch → ....15.118/0006-v5.15-stm32mp-r2.1-DMA.patch
View file
@@ -1,133 +1,15 @@
From 62911b17f33f57875c1b18ed211d5fa0f731ad42 Mon Sep 17 00:00:00 2001
From: Romuald JEANNE <romuald.jeanne@st.com>
Date: Thu, 3 Nov 2022 15:26:34 +0100
Subject: [PATCH 06/22] v5.15-stm32mp-r2 DMA
From a5162908ea9e9ed9fdcb92fc16a979e9ddd6997d Mon Sep 17 00:00:00 2001
From: Romuald Jeanne <romuald.jeanne@st.com>
Date: Tue, 25 Jul 2023 10:39:12 +0200
Subject: [PATCH 06/22] v5.15-stm32mp-r2.1 DMA

Signed-off-by: Romuald JEANNE <romuald.jeanne@st.com>
Signed-off-by: Romuald Jeanne <romuald.jeanne@st.com>
---
.../devicetree/bindings/dma/st,stm32-dma.yaml | 47 +
.../bindings/dma/st,stm32-mdma.yaml | 12 +-
drivers/dma/stm32-dma.c | 1169 +++++++++++++++--
drivers/dma/stm32-dmamux.c | 2 +-
drivers/dma/stm32-mdma.c | 147 ++-
5 files changed, 1240 insertions(+), 137 deletions(-)
drivers/dma/stm32-dma.c | 1169 ++++++++++++++++++++++++++++++++----
drivers/dma/stm32-dmamux.c | 2 +-
drivers/dma/stm32-mdma.c | 147 ++++-
3 files changed, 1185 insertions(+), 133 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 4bf676fd25dc..99351fe0fa17 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -47,6 +47,14 @@ description: |
not wait for the de-assertion of the REQuest, ACK is only managed
by transfer completion. This must only be used on channels
managing transfers for STM32 USART/UART.
+ -bit 30-29: indicated SRAM Buffer size in (2^order)*PAGE_SIZE.
+ Order is given by those 2 bits starting at 0.
+ Valid only whether Intermediate M2M transfer is set.
+ For cyclic, whether Intermediate M2M transfer is chosen, any value can be set:
+ SRAM buffer size will rely on period size and not on this DT value.
+ -bit 31: Intermediate M2M transfer from/to DDR to/from SRAM throughout MDMA
+ 0: MDMA not used to generate an intermediate M2M transfer
+ 1: MDMA used to generate an intermediate M2M transfer.


maintainers:
@@ -82,6 +90,35 @@ properties:
description: if defined, it indicates that the controller
supports memory-to-memory transfer

+ dmas:
+ description: A list of eight dma specifiers, one for each entry in dma-names.
+ Refer to stm32-mdma.yaml for more details.
+ items:
+ - description: DMA channel 0 connected to the MDMA channel specified
+ - description: DMA channel 1 connected to the MDMA channel specified
+ - description: DMA channel 2 connected to the MDMA channel specified
+ - description: DMA channel 3 connected to the MDMA channel specified
+ - description: DMA channel 4 connected to the MDMA channel specified
+ - description: DMA channel 5 connected to the MDMA channel specified
+ - description: DMA channel 6 connected to the MDMA channel specified
+ - description: DMA channel 7 connected to the MDMA channel specified
+
+ dma-names:
+ description: Represents each STM32 DMA channel connected to a STM32 MDMA one.
+ items:
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+ - const: ch4
+ - const: ch5
+ - const: ch6
+ - const: ch7
+
+ memory-region:
+ description: Phandle to a node describing memory to be used for M2M intermediate transfer
+ between DMA and MDMA.
+
required:
- compatible
- reg
@@ -111,6 +148,16 @@ examples:
st,mem2mem;
resets = <&rcc 150>;
dma-requests = <8>;
+ dmas = <&mdma1 8 0x3 0x1200000a 0x40026408 0x00000020 1>,
+ <&mdma1 9 0x3 0x1200000a 0x40026408 0x00000800 1>,
+ <&mdma1 10 0x3 0x1200000a 0x40026408 0x00200000 1>,
+ <&mdma1 11 0x3 0x1200000a 0x40026408 0x08000000 1>,
+ <&mdma1 12 0x3 0x1200000a 0x4002640C 0x00000020 1>,
+ <&mdma1 13 0x3 0x1200000a 0x4002640C 0x00000800 1>,
+ <&mdma1 14 0x3 0x1200000a 0x4002640C 0x00200000 1>,
+ <&mdma1 15 0x3 0x1200000a 0x4002640C 0x08000000 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7";
+ memory-region = <&sram_dmapool>;
};

...
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
index c30be840be1c..c4bb58014374 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
@@ -10,8 +10,8 @@ description: |
The STM32 MDMA is a general-purpose direct memory access controller capable of
supporting 64 independent DMA channels with 256 HW requests.
DMA clients connected to the STM32 MDMA controller must use the format
- described in the dma.txt file, using a five-cell specifier for each channel:
- a phandle to the MDMA controller plus the following five integer cells:
+ described in the dma.txt file, using a six-cell specifier for each channel:
+ a phandle to the MDMA controller plus the following six integer cells:
1. The request line number
2. The priority level
0x0: Low
@@ -48,6 +48,10 @@ description: |
if no HW ack signal is used by the MDMA client
5. A 32bit mask specifying the value to be written to acknowledge the request
if no HW ack signal is used by the MDMA client
+ 6. A bitfield value specifying if the MDMA client wants to generate M2M transfer
+ with HW trigger (1) or not (0). This bitfield should be only enabled for
+ M2M transfer triggered by STM32 DMA client. The memory devices involved in this
+ kind of transfer are SRAM and DDR.

maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
@@ -57,7 +61,7 @@ allOf:

properties:
"#dma-cells":
- const: 5
+ const: 6

compatible:
const: st,stm32h7-mdma
@@ -97,7 +101,7 @@ examples:
interrupts = <122>;
clocks = <&timer_clk>;
resets = <&rcc 992>;
- #dma-cells = <5>;
+ #dma-cells = <6>;
dma-channels = <16>;
dma-requests = <32>;
st,ahb-addr-masks = <0x20000000>, <0x00000000>;
diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
index 7dfc743ac433..7c6078c6c3bf 100644
--- a/drivers/dma/stm32-dma.c
Expand Down

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