-
Notifications
You must be signed in to change notification settings - Fork 2
/
TopLayer.par
201 lines (145 loc) · 8.76 KB
/
TopLayer.par
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
Release 13.2 par O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
FABIANFSSLEB88A:: Sun Dec 04 19:56:01 2011
par -w -intstyle ise -ol high -mt off TopLayer_map.ncd TopLayer.ncd
TopLayer.pcf
Constraints file: TopLayer.pcf.
Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\13.2\ISE_DS\ISE\.
"TopLayer" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.19 2011-06-20".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 110 out of 18,224 1%
Number used as Flip Flops: 109
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 224 out of 9,112 2%
Number used as logic: 223 out of 9,112 2%
Number using O6 output only: 171
Number using O5 output only: 13
Number using O5 and O6: 39
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 1
Number with same-slice register load: 0
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 84 out of 2,278 3%
Number of LUT Flip Flop pairs used: 239
Number with an unused Flip Flop: 141 out of 239 58%
Number with an unused LUT: 15 out of 239 6%
Number of fully used LUT-FF pairs: 83 out of 239 34%
Number of slice register sites lost
to control set restrictions: 0 out of 18,224 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 83 out of 232 35%
Number of LOCed IOBs: 83 out of 83 100%
IOB Latches: 16
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 8 out of 248 3%
Number used as ILOGIC2s: 8
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 8 out of 248 3%
Number used as OLOGIC2s: 8
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 5 secs
Finished initial Timing Analysis. REAL time: 5 secs
WARNING:Par:288 - The signal btns_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 1262 unrouted; REAL time: 5 secs
Phase 2 : 1150 unrouted; REAL time: 6 secs
Phase 3 : 465 unrouted; REAL time: 6 secs
Phase 4 : 465 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 secs
Updating file: TopLayer.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 secs
Total REAL time to Router completion: 8 secs
Total CPU time to Router completion: 8 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X3Y13| No | 38 | 0.064 | 0.910 |
+---------------------+--------------+------+------+------------+-------------+
|divide_clock_by_1000 | | | | | |
| 0/clk_out | Local| | 6 | 0.371 | 0.889 |
+---------------------+--------------+------+------+------------+-------------+
|memory_controller/me | | | | | |
| mcntrl_cfg_finish | Local| | 13 | 2.400 | 2.729 |
+---------------------+--------------+------+------+------------+-------------+
| btnl_btnr_OR_200_o | Local| | 8 | 0.990 | 3.009 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP | 3.729ns| 6.271ns| 0| 0
pin" 100 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 10 secs
Peak Memory Usage: 296 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 3
Number of info messages: 0
Writing design to file TopLayer.ncd
PAR done!