GitHub - Sarthak-Singh/Counter-on-7segment-VLSI: A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

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A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
iseconfig		iseconfig
isim		isim
netgen/synthesis		netgen/synthesis
planAhead_run_1		planAhead_run_1
xlnx_auto_0_xdb		xlnx_auto_0_xdb
xst/work		xst/work
.gitignore		.gitignore
Project_7seg_disp.gise		Project_7seg_disp.gise
Project_7seg_disp.xise		Project_7seg_disp.xise
Seg_Display.cmd_log		Seg_Display.cmd_log
Seg_Display.lso		Seg_Display.lso
Seg_Display.prj		Seg_Display.prj
Seg_Display.syr		Seg_Display.syr
Seg_Display.v		Seg_Display.v
Seg_Display.xst		Seg_Display.xst
Seg_Display_isim_beh.exe		Seg_Display_isim_beh.exe
Seg_Display_stx_beh.prj		Seg_Display_stx_beh.prj
Segment Display Sequence.xlsx		Segment Display Sequence.xlsx
clk_for_d0.v		clk_for_d0.v
clk_for_d0_isim_beh.exe		clk_for_d0_isim_beh.exe
clk_for_d0_stx_beh.prj		clk_for_d0_stx_beh.prj
clk_for_d1.v		clk_for_d1.v
clk_for_d1_stx_beh.prj		clk_for_d1_stx_beh.prj
clk_for_d2.v		clk_for_d2.v
clk_for_d3.v		clk_for_d3.v
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
one_bit_cntr.bgn		one_bit_cntr.bgn
one_bit_cntr.bit		one_bit_cntr.bit
one_bit_cntr.bld		one_bit_cntr.bld
one_bit_cntr.cmd_log		one_bit_cntr.cmd_log
one_bit_cntr.drc		one_bit_cntr.drc
one_bit_cntr.lso		one_bit_cntr.lso
one_bit_cntr.ncd		one_bit_cntr.ncd
one_bit_cntr.ngc		one_bit_cntr.ngc
one_bit_cntr.ngd		one_bit_cntr.ngd
one_bit_cntr.ngr		one_bit_cntr.ngr
one_bit_cntr.pad		one_bit_cntr.pad
one_bit_cntr.par		one_bit_cntr.par
one_bit_cntr.pcf		one_bit_cntr.pcf
one_bit_cntr.prj		one_bit_cntr.prj
one_bit_cntr.ptwx		one_bit_cntr.ptwx
one_bit_cntr.stx		one_bit_cntr.stx
one_bit_cntr.syr		one_bit_cntr.syr
one_bit_cntr.twr		one_bit_cntr.twr
one_bit_cntr.twx		one_bit_cntr.twx
one_bit_cntr.ucf		one_bit_cntr.ucf
one_bit_cntr.unroutes		one_bit_cntr.unroutes
one_bit_cntr.ut		one_bit_cntr.ut
one_bit_cntr.v		one_bit_cntr.v
one_bit_cntr.xpi		one_bit_cntr.xpi
one_bit_cntr.xst		one_bit_cntr.xst
one_bit_cntr_beh.prj		one_bit_cntr_beh.prj
one_bit_cntr_bitgen.xwbt		one_bit_cntr_bitgen.xwbt
one_bit_cntr_guide.ncd		one_bit_cntr_guide.ncd
one_bit_cntr_isim_beh.exe		one_bit_cntr_isim_beh.exe
one_bit_cntr_isim_beh.wdb		one_bit_cntr_isim_beh.wdb
one_bit_cntr_map.map		one_bit_cntr_map.map
one_bit_cntr_map.mrp		one_bit_cntr_map.mrp
one_bit_cntr_map.ncd		one_bit_cntr_map.ncd
one_bit_cntr_map.ngm		one_bit_cntr_map.ngm
one_bit_cntr_map.xrpt		one_bit_cntr_map.xrpt
one_bit_cntr_ngdbuild.xrpt		one_bit_cntr_ngdbuild.xrpt
one_bit_cntr_pad.csv		one_bit_cntr_pad.csv
one_bit_cntr_pad.txt		one_bit_cntr_pad.txt
one_bit_cntr_par.xrpt		one_bit_cntr_par.xrpt
one_bit_cntr_stx_beh.prj		one_bit_cntr_stx_beh.prj
one_bit_cntr_summary.xml		one_bit_cntr_summary.xml
one_bit_cntr_test.v		one_bit_cntr_test.v
one_bit_cntr_test_beh.prj		one_bit_cntr_test_beh.prj
one_bit_cntr_test_isim_beh.exe		one_bit_cntr_test_isim_beh.exe
one_bit_cntr_test_isim_beh.wdb		one_bit_cntr_test_isim_beh.wdb
one_bit_cntr_test_stx_beh.prj		one_bit_cntr_test_stx_beh.prj
one_bit_cntr_usage.xml		one_bit_cntr_usage.xml
one_bit_cntr_xst.xrpt		one_bit_cntr_xst.xrpt
pa.fromHdl.tcl		pa.fromHdl.tcl
seq.v		seq.v
seq_isim_beh.exe		seq_isim_beh.exe
seq_isim_beh1.wdb		seq_isim_beh1.wdb
seq_stx_beh.prj		seq_stx_beh.prj
webtalk_pn.xml		webtalk_pn.xml
xilinxsim.ini		xilinxsim.ini

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A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

verilog vlsi fpga-programming 7-segment-display

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