補充教材學習報告
nand2tetris is a collection of 12 course in building a computer. Starting from the logic gates to creating an operating system capable of running a complicated program like tetris. It's divide into 2 part, the first part covers the hardware portion of the computer, and the second part covers the software layer. In this semester we mostly study the first part of nand2tetris. Somehow i can still understand the logic gates part, but starting from mult and fill, i don't really understand it. I have to watch from youtube and reading other people code to finally understand a little bit, and still can't completely write my owm mult and fill.
I will briefly explain about the basic logic gates that are mostly used. There are 7 basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
Why is it called "AND"? There are only two input and that is "0" and "1" and so is the output. In AND Gate if the output equals to "1" then it means "true" and if the output equals to "0" then it means false. AND Gate require both the input and output equals to "1" to become "TRUE". That is why it's called "AND".
.
.
Same as AND Gate, in OR Gate, there are only two input and output "0" and "1". It's called OR because it require either the input1 OR input2 equals to "1" for the output to become "TRUE". If both the input1 and input2 equals to "1" then the output become "TRUE", only if both input1 and input2 equals to "0" will the output become "FALSE"
.
Using either/or logic the output is "TRUE" if either input1 or input2 equals to "1" and the output is "FALSE" if both the input1 and input2 equals to "0" or both are "1".
.
.
It's more simple in NOT Gate. There are only single input and output. If the input is "0" then the output is "TRUE", and if the input is "1" then the output also "TRUE". So simple isn't it. ^.^
.
NAND gate operates as an AND gate followed by a NOT gate. In NAND Gate the output is "TRUE" if both input1 and input2 equals to "0" and if either input1 or input2 equals to "0" or "1". The output is false if both input1 and input2 equals to "1".
.
.
NOR gate is a combination of OR gate followed by an inverter. In NOR Gate the output is "TRUE" only if both input1 and input2 equals to "0". The output is "FALSE" when either input1 or input2 equals to "1" or "0" and when both input1 and input2 equals to "1".
.
.
XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. The output is "TRUE" if both input1 and input2 equals to "0" or "1". The output is "FALSE" if either input1 or input2 equals to "0" or "1".
.
.
It visually connects the major abstraction levels of a computer (though this slide applies specifically to the HACK platform, other computer platforms work similarly). In the Hardware part, it starts from the combinational of logic gates to produce the CPU, RAM, chipset, and followed by designing the computer architecture and finally assemble it with the Software part to create a computer. The Software starts from writing the program and because the computer can only read machine language, you need to compile it first using VM Translator and the result is the machine language that can be read by your computer. That is my explanation based on my thinking, it's not that perfect but it's more understandable for me that is just recently study this.
To run the program specific tools are needed like: Hardware Simulator: Simulates and tests the logic gates and chips implemented in the HDL (Hardware Description Language). CPU Emulator : Emulates the operation of the Hack computer system. Used to test and run programs written in the Hack machine language, in both its binary and assembly versions. VM Emulator : Used to run and test programs written in the VM language (similar to Java's Bytcode). Assembler : Translates programs from the Hack assembly language to Hack binary code. The resulting code can be executed directly on the Computer chip (in the hardware simulator), or emulated on the supplied CPU Emulator (much faster and more convenient). Compiler : Translates programs written in Jack (a simple, Java-like object-based language) into VM code. The resulting code can run on the supplied VM Emulator. Operating system : Two OS implementations are supplied: (i) a collection of eight .vm class files, written originally in Jack (just like Unix is written in C), and (ii) a faster implementation of all the OS services, embedded in the supplied VM Emulator. Text Comparer : Checks if two input text files are identical, up to white space differences. Used in various projects. In Unix use "diff" instead. In this semester we only used 2 tools and that is Hardware Simulator and CPU Emulator.
RISC-V is an ISA based on reduced instruction set computer (RISC) principles. Have you ever think how a device can read the program that you write? An ISA(Instruction Set Architecture) is designed for this purpose. ISA served as a boundary between hardware and software. It defines a set of basic operations which are needed to run the computer. Including the functional definitions of operations and precise description of how to invoke them. RISC-V is an open standard instruction set architecture based on the established reduced instruction set principles. A general purpose processor is no longer used for the biggest of an innovations. Unlike many other ISA designs, the RISC-V design is provided under open source licenses that don't require payment to use it. The 2 most famous ISA arm and x86, are totally used for different applications. ARM is used for mobile phones, meanwhile x86 is used in computer. Whereas, RISC-V are more suitable to use in specific application fields such as storage, edge computing and AI applications.
RISC-V have more advantages if compare with arm and x86. For example:
- Free. RISC-V is completely free to use.
- Simple. RISC-V is far more smaller than many commercials ISA.
- Modular. RISC-V has a smaller standard base ISA.
- Stable. Base and first standard extensions are fixed, so there are no need for updates.
- Extensibility. Explicit can be added based on extensions. As an example if we compare BOOM implementations of RISC-V with the ARM-32 CORTEX-A9, which is a standard benchmark for embedded microprocessors. If 100000 iterations are run, the ARM finishes in 18.5 seconds whereas the BOOM processor only takes 14.26 seconds. This was achieved because of simpler implementations which allows higher clock frequency.
While there are advantage, there is also disadvantage. Like:
- The ecosystem is not matured enough. RISC-V will have to recreate or adapt to the chip design ecosystem that a dominant ISA has had for a very long time.
- Takes time for implementation. There are a lot of SoC's that are working fine on the RISC-V ISA, but it still needs to be optimized and verified for implementation in real life applications.
For software software, RISC-V is supported by a number of language compilers, including the GNU Compiler Collection (GCC), a popular free-software compiler, and by the Linux operating system (both 32 and 64-bit). And for the hardware support, a number of companies are offering or have announced RISC-V hardware. These range from microcontrollers to SOMs and SOCs that can run Linux, and FPGAs that can include a RISC-V core.
A few notable products include:
1.The BeagleV, a low-cost single board computer than can run Linux 2.The HiFive1 Rev B microcontroller 3.The Seeed Studio Perf-V based on a Xilinx Artix-7 RISC-V FPGA 4.The SparkFun RED-V RedBoard, a microcontroller in an Arduino form factor 5.The LoFive RISC-V SoC evaluation kit
In conclusion, RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. This will encourage innovation and competition at a time when many large manufacturers are buying up their competitors, such as the recent acquisition of Arm Ltd by Nvidia.
Reference:
https://whatis.techtarget.com/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-XNOR