Fixed width immediates

There are a lot of times when encoding AArch64 instructions that we
need to represent an integer value with a custom fixed width. For
example, the offset for a B instruction is 26 bits, so we store an
i32 on the instruction struct and then mask it when we encode.

We've been doing this masking everywhere, which has worked, but
it's getting a bit copy-pasty all over the place. This commit
centralizes that logic to make sure we stay consistent.

yjit/src/asm/arm64/arg/fixed_width.rs

@@ -0,0 +1,57 @@
+// There are many instances in AArch64 instruction encoding where you represent
+// an integer value with a particular bit width that isn't a power of 2. These
+// structs represent the signed and unsigned versions of this kind of encoding,
+// and provide Into<u32> to allow the individual instruction encoding functions
+// to use them easily.
+
+/// Shorten a signed immediate to fit into a compile-time known width.
+pub fn fix_signed_immediate<T: Into<i32>, const WIDTH: usize>(value: T) -> u32 {
+    let value: i32 = value.into();
+    (value as u32) & ((1 << WIDTH) - 1)
+}
+
+/// Shorten an unsigned immediate to fit into a compile-time known width.
+pub fn fix_unsigned_immediate<T: Into<u32>, const WIDTH: usize>(value: T) -> u32 {
+    let value: u32 = value.into();
+    (value & ((1 << WIDTH) - 1))
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_fix_signed_immediate_positive() {
+        let inst = fix_signed_immediate::<i32, 4>(5);
+        let result: u32 = inst.into();
+        assert_eq!(0b0101, result);
+    }
+
+    #[test]
+    fn test_fix_signed_immediate_negative() {
+        let inst = fix_signed_immediate::<i32, 4>(-5);
+        let result: u32 = inst.into();
+        assert_eq!(0b1011, result);
+    }
+
+    #[test]
+    fn test_fix_signed_immediate_truncated() {
+        let inst = fix_signed_immediate::<i32, 4>(-23);
+        let result: u32 = inst.into();
+        assert_eq!(0b1001, result);
+    }
+
+    #[test]
+    fn test_fix_unsigned_immediate() {
+        let inst = fix_unsigned_immediate::<u32, 4>(5);
+        let result: u32 = inst.into();
+        assert_eq!(0b0101, result);
+    }
+
+    #[test]
+    fn test_fix_unsigned_immediate_truncated() {
+        let inst = fix_unsigned_immediate::<u32, 4>(23);
+        let result: u32 = inst.into();
+        assert_eq!(0b0111, result);
+    }
+}

yjit/src/asm/arm64/arg/mod.rs

@@ -3,12 +3,14 @@
 
 mod bitmask_imm;
 mod condition;
+mod fixed_width;
 mod sf;
 mod shifted_imm;
 mod sys_reg;
 
 pub use bitmask_imm::BitmaskImmediate;
 pub use condition::Condition;
+pub use fixed_width::{fix_signed_immediate, fix_unsigned_immediate};
 pub use sf::Sf;
 pub use shifted_imm::ShiftedImmediate;
 pub use sys_reg::SystemRegister;

yjit/src/asm/arm64/inst/branch_cond.rs

@@ -1,4 +1,4 @@
-use super::super::arg::Condition;
+use super::super::arg::{Condition, fix_signed_immediate};
 
 /// The struct that represents an A64 conditional branch instruction that can be
 /// encoded.
@@ -31,12 +31,10 @@ const FAMILY: u32 = 0b101;
 impl From<BranchCond> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: BranchCond) -> Self {
-        let imm19 = (inst.imm19 as u32) & ((1 << 19) - 1);
-
         0
         | (1 << 30)
         | (FAMILY << 26)
-        | (imm19 << 5)
+        | (fix_signed_immediate::<_, 19>(inst.imm19) << 5)
         | (inst.cond as u32)
     }
 }
@@ -66,8 +64,14 @@ mod tests {
     }
 
     #[test]
-    fn test_b_ne_neg() {
-        let result: u32 = BranchCond::bcond(Condition::NE, -128).into();
-        assert_eq!(0x54fffc01, result);
+    fn test_b_eq_max() {
+        let result: u32 = BranchCond::bcond(Condition::EQ, (1 << 20) - 4).into();
+        assert_eq!(0x547fffe0, result);
+    }
+
+    #[test]
+    fn test_b_eq_min() {
+        let result: u32 = BranchCond::bcond(Condition::EQ, -(1 << 20)).into();
+        assert_eq!(0x54800000, result);
     }
 }

yjit/src/asm/arm64/inst/call.rs

@@ -1,3 +1,5 @@
+use super::super::arg::fix_signed_immediate;
+
 /// The operation to perform for this instruction.
 enum Op {
     /// Branch directly, with a hint that this is not a subroutine call or
@@ -45,12 +47,10 @@ const FAMILY: u32 = 0b101;
 impl From<Call> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: Call) -> Self {
-        let imm26 = (inst.imm26 as u32) & ((1 << 26) - 1);
-
         0
         | ((inst.op as u32) << 31)
         | (FAMILY << 26)
-        | imm26
+        | fix_signed_immediate::<_, 26>(inst.imm26)
     }
 }
 
@@ -92,13 +92,13 @@ mod tests {
 
     #[test]
     fn test_b_positive() {
-        let result: u32 = Call::b(256).into();
-        assert_eq!(0x14000100, result);
+        let result: u32 = Call::b((1 << 25) - 1).into();
+        assert_eq!(0x15ffffff, result);
     }
 
     #[test]
     fn test_b_negative() {
-        let result: u32 = Call::b(-256).into();
-        assert_eq!(0x17ffff00, result);
+        let result: u32 = Call::b(-(1 << 25)).into();
+        assert_eq!(0x16000000, result);
     }
 }

yjit/src/asm/arm64/inst/data_reg.rs

@@ -1,4 +1,4 @@
-use super::super::arg::Sf;
+use super::super::arg::{Sf, fix_unsigned_immediate};
 
 /// The operation being performed by this instruction.
 enum Op {
@@ -129,8 +129,6 @@ const FAMILY: u32 = 0b0101;
 impl From<DataReg> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: DataReg) -> Self {
-        let imm6 = (inst.imm6 as u32) & ((1 << 6) - 1);
-
         0
         | ((inst.sf as u32) << 31)
         | ((inst.op as u32) << 30)
@@ -139,7 +137,7 @@ impl From<DataReg> for u32 {
         | (1 << 24)
         | ((inst.shift as u32) << 22)
         | ((inst.rm as u32) << 16)
-        | (imm6 << 10)
+        | (fix_unsigned_immediate::<_, 6>(inst.imm6) << 10)
         | ((inst.rn as u32) << 5)
         | inst.rd as u32
     }

yjit/src/asm/arm64/inst/load_literal.rs

@@ -1,3 +1,5 @@
+use super::super::arg::fix_signed_immediate;
+
 /// The size of the operands being operated on.
 enum Opc {
     Size32 = 0b00,
@@ -50,13 +52,11 @@ const FAMILY: u32 = 0b0100;
 impl From<LoadLiteral> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: LoadLiteral) -> Self {
-        let imm19 = (inst.imm19 as u32) & ((1 << 19) - 1);
-
         0
         | ((inst.opc as u32) << 30)
         | (1 << 28)
         | (FAMILY << 25)
-        | (imm19 << 5)
+        | (fix_signed_immediate::<_, 19>(inst.imm19) << 5)
         | (inst.rt as u32)
     }
 }

yjit/src/asm/arm64/inst/load_store.rs

@@ -1,3 +1,5 @@
+use super::super::arg::fix_signed_immediate;
+
 /// The size of the operands being operated on.
 enum Size {
     Size32 = 0b10,
@@ -110,14 +112,12 @@ const FAMILY: u32 = 0b0100;
 impl From<LoadStore> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: LoadStore) -> Self {
-        let imm9 = (inst.imm9 as u32) & ((1 << 9) - 1);
-
         0
         | ((inst.size as u32) << 30)
         | (0b11 << 28)
         | (FAMILY << 25)
         | ((inst.opc as u32) << 22)
-        | (imm9 << 12)
+        | (fix_signed_immediate::<_, 9>(inst.imm9) << 12)
         | ((inst.idx as u32) << 10)
         | ((inst.rn as u32) << 5)
         | (inst.rt as u32)

yjit/src/asm/arm64/inst/logical_reg.rs

@@ -1,4 +1,4 @@
-use super::super::arg::Sf;
+use super::super::arg::{Sf, fix_unsigned_immediate};
 
 /// Whether or not this is a NOT instruction.
 enum N {
@@ -124,16 +124,14 @@ const FAMILY: u32 = 0b0101;
 impl From<LogicalReg> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: LogicalReg) -> Self {
-        let imm6 = (inst.imm6 as u32) & ((1 << 6) - 1);
-
         0
         | ((inst.sf as u32) << 31)
         | ((inst.opc as u32) << 29)
         | (FAMILY << 25)
         | ((inst.shift as u32) << 22)
         | ((inst.n as u32) << 21)
         | ((inst.rm as u32) << 16)
-        | (imm6 << 10)
+        | (fix_unsigned_immediate::<_, 6>(inst.imm6) << 10)
         | ((inst.rn as u32) << 5)
         | inst.rd as u32
     }

yjit/src/asm/arm64/inst/reg_pair.rs

@@ -1,3 +1,5 @@
+use super::super::arg::fix_signed_immediate;
+
 /// The operation to perform for this instruction.
 enum Opc {
     /// When the registers are 32-bits wide.
@@ -114,18 +116,12 @@ const FAMILY: u32 = 0b0100;
 impl From<RegisterPair> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: RegisterPair) -> Self {
-        let mut imm7 = (inst.imm7 as u32) & ((1 << 7) - 1);
-
-        if inst.imm7 < 0 {
-            imm7 |= 1 << 6;
-        }
-
         0
         | ((inst.opc as u32) << 30)
         | (1 << 29)
         | (FAMILY << 25)
         | ((inst.index as u32) << 22)
-        | (imm7 << 15)
+        | (fix_signed_immediate::<_, 7>(inst.imm7) << 15)
         | ((inst.rt2 as u32) << 10)
         | ((inst.rn as u32) << 5)
         | (inst.rt1 as u32)

yjit/src/asm/arm64/inst/sbfm.rs

@@ -1,4 +1,4 @@
-use super::super::arg::Sf;
+use super::super::arg::{Sf, fix_unsigned_immediate};
 
 /// The struct that represents an A64 signed bitfield move instruction that can
 /// be encoded.
@@ -56,16 +56,13 @@ const FAMILY: u32 = 0b1001;
 impl From<SBFM> for u32 {
     /// Convert an instruction into a 32-bit value.
     fn from(inst: SBFM) -> Self {
-        let immr = (inst.immr as u32) & ((1 << 6) - 1);
-        let imms = (inst.imms as u32) & ((1 << 6) - 1);
-
         0
         | ((inst.sf as u32) << 31)
         | (FAMILY << 25)
         | (1 << 24)
         | ((inst.n as u32) << 22)
-        | (immr << 16)
-        | (imms << 10)
+        | (fix_unsigned_immediate::<_, 6>(inst.immr) << 16)
+        | (fix_unsigned_immediate::<_, 6>(inst.imms) << 10)
         | ((inst.rn as u32) << 5)
         | inst.rd as u32
     }