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Computational Lithography
Lukas Chrostowski edited this page Dec 3, 2018
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1 revision
Developed by Stephen Lin, UBC, 2018
Building on previous paper by Xu Wang, Lukas Chrostowski.
Create a layout with
- Layer 1/0 for regular silicon
- Layer 1/69 for silicon to be lithography simulated
Upload the layout via openEBL:
- http://linkedin.com/pulse/openebl-fabrication-test-passive-silicon-photonic-lukas-chrostowski/
- http://upload.siepic.ubc.ca/openEBL.php
Wait 5 minutes
Download the merged and litho simulated layout
- http://upload.siepic.ubc.ca/openEBL/openEBL-litho.gds
- The 1/69 shapes, after litho simulation, will appear on 1/0.