GitHub - SiavashShams/ARM-Processor_With_Forwarding_And_SRAM: The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

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The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
Quartus		Quartus
ALU.sv		ALU.sv
ALU.sv.bak		ALU.sv.bak
ARM_PROCESSOR.cr.mti		ARM_PROCESSOR.cr.mti
ARM_PROCESSOR.mpf		ARM_PROCESSOR.mpf
ARM_PROCESSOR.sv		ARM_PROCESSOR.sv
ARM_PROCESSOR.sv.bak		ARM_PROCESSOR.sv.bak
Condition_Check.sv		Condition_Check.sv
Condition_Check.sv.bak		Condition_Check.sv.bak
Controller.sv		Controller.sv
DE2_pin_assignments.csv		DE2_pin_assignments.csv
EXE_Stage.sv		EXE_Stage.sv
EXE_Stage_Reg.sv		EXE_Stage_Reg.sv
Forwaring_Unit.sv		Forwaring_Unit.sv
Hazard_Detection_Unit.sv		Hazard_Detection_Unit.sv
ID_Stage.sv		ID_Stage.sv
ID_Stage.sv.bak		ID_Stage.sv.bak
ID_Stage_Reg.sv		ID_Stage_Reg.sv
IF_Stage.sv		IF_Stage.sv
IF_Stage.sv.bak		IF_Stage.sv.bak
IF_Stage_Reg.sv		IF_Stage_Reg.sv
IF_Stage_Reg.sv.bak		IF_Stage_Reg.sv.bak
IF_Stage_TB.sv		IF_Stage_TB.sv
IF_Stage_TB.sv.bak		IF_Stage_TB.sv.bak
Inst_Mem.sv		Inst_Mem.sv
Mem_Stage.sv		Mem_Stage.sv
Mem_Stage.sv.bak		Mem_Stage.sv.bak
Mem_Stage_Reg.sv		Mem_Stage_Reg.sv
RegisterFile.sv		RegisterFile.sv
Register_File.sv		Register_File.sv
Register_File.sv.bak		Register_File.sv.bak
Report.pdf		Report.pdf
SRAM.sv		SRAM.sv
Sram_Controller.sv		Sram_Controller.sv
TB.sv		TB.sv
TB.sv.bak		TB.sv.bak
Val2Gen.sv		Val2Gen.sv
Val2Gen_TB.sv		Val2Gen_TB.sv
WB_Stage.sv		WB_Stage.sv
inst_mem.txt		inst_mem.txt
transcript		transcript
vsim.wlf		vsim.wlf

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The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

arm fpga sram forwarding modelsim quartus

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