added comments

matter/si91x/siwx917/BRD4338A/support/hal/rsi_hal_mcu_m4.c

@@ -23,7 +23,7 @@
 #include "rsi_debug.h"
 #include "rsi_rom_egpio.h"
 
-#define SOC_PLL_REF_FREQUENCY 40000000// /* PLL input REFERENCE clock 32MHZ */
+#define SOC_PLL_REF_FREQUENCY 40000000 // /* PLL input REFERENCE clock 40MHZ */
 
 // Note: Change this macro to required PLL frequency in hertz
 #define PS4_SOC_FREQ 180000000 /* PLL out clock 180MHz */
@@ -33,29 +33,30 @@
 
 /* QSPI clock config params */
 #define INTF_PLL_500_CTRL_VALUE 0xD900
-#define INTF_PLL_CLK 80000000 /* PLL out clock 80 MHz */
+#define INTF_PLL_CLK            80000000 /* PLL out clock 80 MHz */
 
-#define PMU_GOOD_TIME 31  /*Duration in us*/
+#define PMU_GOOD_TIME  31 /*Duration in us*/
 #define XTAL_GOOD_TIME 31 /*Duration in us*/
 
 /*Pre-fetch and regestring */
-#define ICACHE2_ADDR_TRANSLATE_1_REG *(volatile uint32_t *)(0x20280000 + 0x24)
+#define ICACHE2_ADDR_TRANSLATE_1_REG  *(volatile uint32_t *)(0x20280000 + 0x24)
 #define MISC_CFG_SRAM_REDUNDANCY_CTRL *(volatile uint32_t *)(0x46008000 + 0x18)
-#define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44)
-#define MISC_QUASI_SYNC_MODE *(volatile uint32_t *)(0x46008000 + 0x84)
+#define MISC_CONFIG_MISC_CTRL1        *(volatile uint32_t *)(0x46008000 + 0x44)
+#define MISC_QUASI_SYNC_MODE          *(volatile uint32_t *)(0x46008000 + 0x84)
 
 void sl_button_on_change(uint8_t btn, uint8_t btnAction);
 
-int soc_pll_config(void) {
+int soc_pll_config(void)
+{
   int32_t status = RSI_OK;
 
   RSI_CLK_M4SocClkConfig(M4CLK, M4_ULPREFCLK, 0);
-    // Configures the required registers for 180 Mhz clock in PS4
+  // Configures the required registers for 180 Mhz clock in PS4
   RSI_PS_PS4SetRegisters();
-    // Configure the PLL frequency
-    // Configure the SOC PLL to 180MHz
+  // Configure the PLL frequency
+  // Configure the SOC PLL to 180MHz
   RSI_CLK_SetSocPllFreq(M4CLK, PS4_SOC_FREQ, SOC_PLL_REF_FREQUENCY);
-    // Switch M4 clock to PLL clock for speed operations
+  // Switch M4 clock to PLL clock for speed operations
   RSI_CLK_M4SocClkConfig(M4CLK, M4_SOCPLLCLK, 0);
 
   SysTick_Config(SystemCoreClock / 1000);
@@ -64,7 +65,7 @@ int soc_pll_config(void) {
 #ifdef SWITCH_QSPI_TO_SOC_PLL
   /* program intf pll to 160Mhz */
   SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = INTF_PLL_500_CTRL_VALUE;
-  status = RSI_CLK_SetIntfPllFreq(M4CLK, INTF_PLL_CLK, SOC_PLL_REF_FREQUENCY);
+  status                                  = RSI_CLK_SetIntfPllFreq(M4CLK, INTF_PLL_CLK, SOC_PLL_REF_FREQUENCY);
   if (status != RSI_OK) {
     SILABS_LOG("Failed to Config Interface PLL Clock, status:%d", status);
   } else {
@@ -76,8 +77,8 @@ int soc_pll_config(void) {
   return 0;
 }
 
-void sl_si91x_button_isr(uint8_t pin, uint8_t state) {
-  (pin == SL_BUTTON_BTN0_PIN)
-      ? sl_button_on_change(SL_BUTTON_BTN0_NUMBER, !state)
-      : sl_button_on_change(SL_BUTTON_BTN1_NUMBER, !state);
+void sl_si91x_button_isr(uint8_t pin, uint8_t state)
+{
+  (pin == SL_BUTTON_BTN0_PIN) ? sl_button_on_change(SL_BUTTON_BTN0_NUMBER, !state)
+                              : sl_button_on_change(SL_BUTTON_BTN1_NUMBER, !state);
 }