Popular repositories Loading

1. dual_port_ram dual_port_ram Public

   Designed a 256‐bit x 8‐bit synchronous dual port RAM with any combination of Read and Write operations in the same clock cycle using Verilog HDL.

   Verilog

2. smart_car_parking_system smart_car_parking_system Public

   Designed and implemented a password‐controlled car parking system using Verilog HDL.

   Verilog

3. accident_avoidance_sytem accident_avoidance_sytem Public

   Designed and simulated an accident avoidance system using ultrasonic sensor on TinkerCad.

   C

4. Spotify-EDA Spotify-EDA Public

   Jupyter Notebook

5. Titanic Titanic Public

   Jupyter Notebook

6. case-study case-study Public

   Product Teardown of a loan assist app by SpringMoney