fix: chisel3 pr chipsalliance#2758

+ Replace getPorts with DataMirror.modulePorts;
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;

src/main/scala/amba/ahb/AHBLite.scala

@@ -28,8 +28,8 @@ class AHBLite()(implicit p: Parameters) extends LazyModule {
       out.hprot  := in.hprot
       out.haddr  := in.haddr
       out.hwdata := in.hwdata
-      out.hauser :<> in.hauser
-      in.hduser :<> out.hduser
+      out.hauser :<>= in.hauser
+      in.hduser :<>= out.hduser
       in.hrdata := out.hrdata
     }
   }

src/main/scala/amba/ahb/Xbar.scala

@@ -46,7 +46,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
 
       when (in.hready) { d_sel := a_sel }
       (a_sel zip io_out) foreach { case (sel, out) =>
-        out :<> in
+        out :<>= in
         out.hsel := in.hsel && sel
         out.hmaster.map { _ := 0.U }
       }

src/main/scala/amba/apb/Xbar.scala

@@ -43,7 +43,7 @@ class APBFanout()(implicit p: Parameters) extends LazyModule {
 
       val sel = VecInit(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
       (sel zip io_out) foreach { case (sel, out) =>
-        out :<> in
+        out :<>= in
         out.psel    := sel && in.psel
         out.penable := sel && in.penable
       }

src/main/scala/amba/axi4/Credited.scala

@@ -18,11 +18,11 @@ class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) exten
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out.aw :<> in.aw.pipeline(delay.aw)
-      out.w :<> in.w.pipeline(delay.w)
-      in.b :<> out.b.pipeline(delay.b)
-      out.ar :<> in.ar.pipeline(delay.ar)
-      in.r :<> out.r.pipeline(delay.r)
+      out.aw :<>= in.aw.pipeline(delay.aw)
+      out.w :<>= in.w.pipeline(delay.w)
+      in.b :<>= out.b.pipeline(delay.b)
+      out.ar :<>= in.ar.pipeline(delay.ar)
+      in.r :<>= out.r.pipeline(delay.r)
     }
   }
 }
@@ -43,11 +43,11 @@ class AXI4CreditedSource(delay: AXI4CreditedDelay)(implicit p: Parameters) exten
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
       val tld = edgeOut.delay
-      out.aw :<> CreditedIO.fromSender(in.aw, tld.aw.total).pipeline(delay.aw)
-      out.w :<> CreditedIO.fromSender(in.w, tld.w.total).pipeline(delay.w)
-      in.b :<> out.b.pipeline(delay.b).toReceiver(tld.b.total)
-      out.ar :<> CreditedIO.fromSender(in.ar, tld.ar.total).pipeline(delay.ar)
-      in.r :<> out.r.pipeline(delay.r).toReceiver(tld.r.total)
+      out.aw :<>= CreditedIO.fromSender(in.aw, tld.aw.total).pipeline(delay.aw)
+      out.w :<>= CreditedIO.fromSender(in.w, tld.w.total).pipeline(delay.w)
+      in.b :<>= out.b.pipeline(delay.b).toReceiver(tld.b.total)
+      out.ar :<>= CreditedIO.fromSender(in.ar, tld.ar.total).pipeline(delay.ar)
+      in.r :<>= out.r.pipeline(delay.r).toReceiver(tld.r.total)
     }
   }
 }
@@ -68,11 +68,11 @@ class AXI4CreditedSink(delay: AXI4CreditedDelay)(implicit p: Parameters) extends
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
       val tld = edgeIn.delay
-      out.aw :<> in.aw.pipeline(delay.aw).toReceiver(tld.aw.total)
-      out.w :<> in.w.pipeline(delay.w).toReceiver(tld.w.total)
-      in.b :<> CreditedIO.fromSender(out.b, tld.b.total).pipeline(delay.b)
-      out.ar :<> in.ar.pipeline(delay.ar).toReceiver(tld.ar.total)
-      in.r :<> CreditedIO.fromSender(out.r, tld.r.total).pipeline(delay.r)
+      out.aw :<>= in.aw.pipeline(delay.aw).toReceiver(tld.aw.total)
+      out.w :<>= in.w.pipeline(delay.w).toReceiver(tld.w.total)
+      in.b :<>= CreditedIO.fromSender(out.b, tld.b.total).pipeline(delay.b)
+      out.ar :<>= in.ar.pipeline(delay.ar).toReceiver(tld.ar.total)
+      in.r :<>= CreditedIO.fromSender(out.r, tld.r.total).pipeline(delay.r)
     }
   }
 }

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -47,14 +47,14 @@ class AXI4Deinterleaver(maxReadBytes: Int, buffer: BufferParams = BufferParams.d
       val beats = maxBeats(edgeOut.slave)
 
       // This adapter passes through the AR/AW control + W/B write data channels
-      out.ar :<> in.ar
-      out.aw :<> in.aw
-      out.w :<> in.w
-      in.b :<> out.b
+      out.ar :<>= in.ar
+      out.aw :<>= in.aw
+      out.w :<>= in.w
+      in.b :<>= out.b
 
       // Only the R channel has the possibility of being changed
       if (nothingToDeinterleave(edgeOut.slave)) {
-        in.r.asInstanceOf[ReadyValidIO[AXI4BundleR]] :<> buffer.irrevocable(out.r)
+        in.r.asInstanceOf[ReadyValidIO[AXI4BundleR]] :<>= buffer.irrevocable(out.r)
       } else {
         // We only care to deinterleave ids that are actually in use
         val maxFlightPerId = Seq.tabulate(endId) { i =>

src/main/scala/amba/axi4/Filter.scala

@@ -32,7 +32,7 @@ class AXI4Filter(
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out :<> in
+      out :<>= in
     }
   }
 }

src/main/scala/amba/axi4/Fragmenter.scala

@@ -147,7 +147,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       val in_w = Queue.irrevocable(in.w, 1, flow=true)
 
       // AR flow control; super easy
-      out.ar :<>: in_ar
+      (out.ar: Data).waiveAll :<>= (in_ar: Data).waiveAll
       out.ar.bits.echo(AXI4FragLast) := ar_last
 
       // When does W channel start counting a new transfer
@@ -161,7 +161,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       out.aw.valid := in_aw.valid && (wbeats_ready || wbeats_latched)
       in_aw.ready := out.aw.ready && (wbeats_ready || wbeats_latched)
       wbeats_valid := in_aw.valid && !wbeats_latched
-      out.aw.bits :<>: in_aw.bits
+      (out.aw.bits: Data).waiveAll :<>= (in_aw.bits: Data).waiveAll
       out.aw.bits.echo(AXI4FragLast) := aw_last
 
       // We need to inject 'last' into the W channel fragments, count!
@@ -183,12 +183,12 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
       // R flow control
       val r_last = out.r.bits.echo(AXI4FragLast)
-      in.r :<> out.r
+      (in.r: Data).waiveAll :<>= (out.r: Data).waiveAll
       in.r.bits.last := out.r.bits.last && r_last
 
       // B flow control
       val b_last = out.b.bits.echo(AXI4FragLast)
-      in.b :<> out.b
+      (in.b: Data).waiveAll :<>= (out.b: Data).waiveAll
       in.b.valid := out.b.valid && b_last
       out.b.ready := in.b.ready || !b_last
 

src/main/scala/amba/axi4/IdIndexer.scala

@@ -60,11 +60,11 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
 
       // Leave everything mostly untouched
-      out.ar :<> in.ar
-      out.aw :<> in.aw
-      out.w :<> in.w
-      in.b :<> out.b
-      in.r :<> out.r
+      (out.ar: Data).waiveAll :<>= (in.ar: Data).waiveAll.squeezeAll
+      (out.aw: Data).waiveAll :<>= (in.aw: Data).waiveAll.squeezeAll
+      out.w :<>= in.w
+      (in.b: Data).waiveAll :<>= (out.b: Data).waiveAll.squeezeAll
+      (in.r: Data).waiveAll :<>= (out.r: Data).waiveAll.squeezeAll
 
       val bits = log2Ceil(edgeIn.master.endId) - idBits
       if (bits > 0) {

src/main/scala/amba/axi4/ToTL.scala

@@ -110,7 +110,7 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       r_out.valid := in.ar.valid
       r_out.bits :<= edgeOut.Get(r_id, r_addr, r_size)._2
 
-      r_out.bits.user :<= in.ar.bits.user
+      (r_out.bits.user: Data).waiveAll :<= (in.ar.bits.user: Data).waiveAll
       r_out.bits.user.lift(AMBAProt).foreach { rprot =>
         rprot.privileged :=  in.ar.bits.prot(0)
         rprot.secure     := !in.ar.bits.prot(1)
@@ -146,7 +146,7 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       w_out.bits :<= edgeOut.Put(w_id, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
       in.w.bits.user.lift(AMBACorrupt).foreach { w_out.bits.corrupt := _ }
 
-      w_out.bits.user :<= in.aw.bits.user
+     (w_out.bits.user: Data).waiveAll :<= (in.aw.bits.user: Data).waiveAll
       w_out.bits.user.lift(AMBAProt).foreach { wprot =>
         wprot.privileged :=  in.aw.bits.prot(0)
         wprot.secure     := !in.aw.bits.prot(1)
@@ -182,7 +182,7 @@ class AXI4ToTL(wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule
       ok_r.bits.user :<= out.d.bits.user
 
       // AXI4 needs irrevocable behaviour
-      in.r :<> Queue.irrevocable(ok_r, 1, flow=true)
+      in.r :<>= Queue.irrevocable(ok_r, 1, flow=true)
 
       ok_b.bits.id   := out.d.bits.source >> addedBits
       ok_b.bits.resp := d_resp

src/main/scala/amba/axi4/UserYanker.scala

@@ -56,13 +56,13 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       val ar_ready = Vec(rqueues.map(_.enq.ready))(arid)
       in .ar.ready := out.ar.ready && ar_ready
       out.ar.valid := in .ar.valid && ar_ready
-      out.ar.bits :<= in .ar.bits
+      (out.ar.bits: Data).waiveAll :<= (in .ar.bits: Data).waiveAll
 
       val rid = out.r.bits.id
       val r_valid = Vec(rqueues.map(_.deq.valid))(rid)
       val r_bits = Vec(rqueues.map(_.deq.bits))(rid)
       assert (!out.r.valid || r_valid) // Q must be ready faster than the response
-      in.r :<> out.r
+      (in.r: Data).waiveAll :<>= (out.r: Data).waiveAll
       in.r.bits.echo :<= r_bits
 
       val arsel = UIntToOH(arid, edgeIn.master.endId).asBools
@@ -77,13 +77,13 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
       val aw_ready = Vec(wqueues.map(_.enq.ready))(awid)
       in .aw.ready := out.aw.ready && aw_ready
       out.aw.valid := in .aw.valid && aw_ready
-      out.aw.bits :<= in .aw.bits
+      (out.aw.bits: Data).waiveAll :<= (in .aw.bits: Data).waiveAll
 
       val bid = out.b.bits.id
       val b_valid = Vec(wqueues.map(_.deq.valid))(bid)
       val b_bits = Vec(wqueues.map(_.deq.bits))(bid)
       assert (!out.b.valid || b_valid) // Q must be ready faster than the response
-      in.b :<> out.b
+      (in.b: Data).waiveAll :<>= (out.b: Data).waiveAll
       in.b.bits.echo :<= b_bits
 
       val awsel = UIntToOH(awid, edgeIn.master.endId).asBools
@@ -94,7 +94,7 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
         q.enq.bits :<= in.aw.bits.echo
       }
 
-      out.w :<> in.w
+      out.w :<>= in.w
     }
   }
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -85,7 +85,7 @@ class AXI4Xbar(
     // Transform input bundles
     val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i) :<> io_in(i)
+      in(i) :<>= io_in(i)
 
       // Handle size = 1 gracefully (Chisel3 empty range is broken)
       def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
@@ -168,7 +168,7 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i) :<> out(i)
+      io_out(i) :<>= out(i)
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source

src/main/scala/amba/axis/Buffer.scala

@@ -2,6 +2,7 @@
 
 package freechips.rocketchip.amba.axis
 
+import chisel3._
 import freechips.rocketchip.config._
 import freechips.rocketchip.util._
 import freechips.rocketchip.diplomacy._
@@ -12,7 +13,7 @@ class AXISBuffer(val params: BufferParams)(implicit p: Parameters) extends LazyM
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out :<>: params.irrevocable(in)
+      (out: Data).waiveAll :<>= (params.irrevocable(in): Data).waiveAll
     }
   }
 }

src/main/scala/amba/axis/Xbar.scala

@@ -42,14 +42,14 @@ class AXISXbar(beatBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin)(
     // Transform input bundle sources (dest uses global namespace on both sides)
     val in = Wire(Vec(io_in.size, AXISBundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i) :<> io_in(i)
+      in(i) :<>= io_in(i)
       in(i).bits.lift(AXISId) foreach { _ := io_in(i).bits.id | inputIdRanges(i).start.U }
     }
 
     // Transform output bundle sinks (id use global namespace on both sides)
     val out = Wire(Vec(io_out.size, AXISBundle(wide_bundle)))
     for (o <- 0 until out.size) {
-      io_out(o) :<> out(o)
+      io_out(o) :<>= out(o)
       io_out(o).bits.lift(AXISDest) foreach { _ := trim(out(o).bits.dest, outputIdRanges(o).size) }
     }
 
@@ -77,7 +77,7 @@ object AXISXbar
     if (sources.isEmpty) {
       sink.valid := false.B
     } else if (sources.size == 1) {
-      sink :<> sources.head
+      sink :<>= sources.head
     } else {
       // The number of beats which remain to be sent
       val idle = RegInit(true.B)

src/main/scala/diplomacy/CloneModule.scala

@@ -23,7 +23,7 @@ class ClonePorts protected[shim](elts: Data*) extends Record
 class CloneModule private (model: RawModule) extends BlackBox
 {
   override def desiredName = model.name
-  val io = IO(new ClonePorts(model.getPorts.map(_.id): _*))
+  val io = IO(new ClonePorts(DataMirror.modulePorts(model).map(_._2): _*))
 }
 
 object CloneModule

src/main/scala/tilelink/Arbiter.scala

@@ -68,7 +68,7 @@ object TLArbiter
     applyCancel(policy = policy)(
       sink = sink_ACancel,
       sources = sources_ACancel:_*)
-    sink :<> sink_ACancel.asDecoupled()
+    sink :<>= sink_ACancel.asDecoupled()
   }
 
   def applyCancel[T <: Data](policy: Policy)(sink: ReadyValidCancel[T], sources: (UInt, ReadyValidCancel[T])*): Unit = {
@@ -77,7 +77,7 @@ object TLArbiter
       sink.lateCancel := DontCare
       sink.bits       := DontCare
     } else if (sources.size == 1) {
-      sink :<> sources.head._2
+      sink :<>= sources.head._2
     } else {
       val pairs = sources.toList
       val beatsIn = pairs.map(_._1)

src/main/scala/tilelink/BlockDuringReset.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.tilelink
 import chisel3._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util.{BlockDuringReset, EnhancedChisel3Assign}
+import freechips.rocketchip.util.{BlockDuringReset}
 
 /** BlockDuringReset ensures that no channel admits to be ready or valid while reset is raised. */
 class TLBlockDuringReset(stretchResetCycles: Int = 0)
@@ -16,12 +16,12 @@ class TLBlockDuringReset(stretchResetCycles: Int = 0)
   lazy val module = new Impl
   class Impl extends LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out.a :<> BlockDuringReset(in .a, stretchResetCycles)
-      in .d :<> BlockDuringReset(out.d, stretchResetCycles)
+      out.a :<>= BlockDuringReset(in .a, stretchResetCycles)
+      in .d :<>= BlockDuringReset(out.d, stretchResetCycles)
       if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
-        in .b :<> BlockDuringReset(out.b, stretchResetCycles)
-        out.c :<> BlockDuringReset(in .c, stretchResetCycles)
-        out.e :<> BlockDuringReset(in .e, stretchResetCycles)
+        in .b :<>= BlockDuringReset(out.b, stretchResetCycles)
+        out.c :<>= BlockDuringReset(in .c, stretchResetCycles)
+        out.e :<>= BlockDuringReset(in .e, stretchResetCycles)
       } else {
         in.b.valid  := false.B
         in.c.ready  := true.B

src/main/scala/tilelink/Bundle_ACancel.scala

@@ -21,11 +21,11 @@ class TLBundle_ACancel(val params: TLBundleParameters) extends Record
   /** Down-converts a TLBundle_ACancel to a plain TLBundle, dropping early/late timing split. */
   def asDecoupled(): TLBundle = {
     val out = Wire(new TLBundle(params))
-    out.a :<> a.asDecoupled()
-    b :<> out.b
-    out.c :<> c
-    d :<> out.d
-    out.e :<> e
+    out.a :<>= a.asDecoupled()
+    b :<>= out.b
+    out.c :<>= c
+    d :<>= out.d
+    out.e :<>= e
     out
   }
 
@@ -55,10 +55,10 @@ object TLBundle_ACancel
     out.a.lateCancel := false.B
     out.a.bits := in.a.bits
     in.a.ready := out.a.ready
-    in.b :<> out.b
-    out.c :<> in.c
-    in.d :<> out.d
-    out.e :<> in.e
+    in.b :<>= out.b
+    out.c :<>= in.c
+    in.d :<>= out.d
+    out.e :<>= in.e
     out
   }
 }