Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

compile warning: DCache CreditedCrossing #2758

Merged
merged 1 commit into from Dec 7, 2020
Merged

compile warning: DCache CreditedCrossing #2758

merged 1 commit into from Dec 7, 2020

Conversation

ingallsj
Copy link
Contributor

@ingallsj ingallsj commented Dec 6, 2020

Related issue: introduced by #2555

Type of change: paying off technical debt

Impact: no functional change

Development Phase: implementation

Release Notes
fix compile warnings:

[warn] /rocket-chip/src/main/scala/rocket/DCache.scala:141:31: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]     val a_queue_depth = outer.crossing match {
[warn]                               ^
[warn] /rocket-chip/src/main/scala/rocket/DCache.scala:1064:32: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]     val beatsBeforeEnd = outer.crossing match {
[warn]                                ^

@ingallsj ingallsj merged commit 16ba330 into master Dec 7, 2020
@ingallsj ingallsj deleted the Warn-CreditedCrossing branch December 7, 2020 20:35
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Dec 26, 2022
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
87e69eb 
+ Remove parenthesized forms of asUInt(), asSInt(), orR(), andR(), zext();
+ Replace getPorts with DataMirror.modulePorts;
+ Replace MultiIOModule with Module;
+ Remove stop with non-zero return code;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 5, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
65d58a0 
+ Remove parenthesized forms of asUInt(), asSInt(), orR(), andR(), zext();
+ Replace getPorts with DataMirror.modulePorts;
+ Replace MultiIOModule with Module;
+ Remove stop with non-zero return code;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 5, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
2f94ae7 
+ Replace MultiIOModule with Module;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 5, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
0eb6b62 
+ Remove parenthesized forms of asUInt(), asSInt(), orR(), andR(), zext();
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 5, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
bf452bc 
+ Replace getPorts with DataMirror.modulePorts;
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 7, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
3c4318a 
+ Replace MultiIOModule with Module;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 7, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
0fefab1 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Jan 7, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
e69b1db 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
ZenithalHourlyRate pushed a commit that referenced this pull request Feb 10, 2023
@SingularityKChen @ZenithalHourlyRate
fix: chisel3 pr #2758
7fb5edf 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
sequencer added a commit that referenced this pull request Feb 15, 2023
@sequencer
Revert "fix: chisel3 pr #2758"
6ba9a3b 
This reverts commit 7fb5edf.
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Feb 17, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
d4e8447 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Feb 17, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
0a58e7a 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Feb 17, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
ce91595 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Feb 17, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
8d7bfd4 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
SingularityKChen added a commit to SingularityKChen/rocket-chip that referenced this pull request Feb 27, 2023
@SingularityKChen
fix: chisel3 pr chipsalliance#2758
b16bdb9 
+ remove EnhancedChisel3Assign;
+ using .waiveAll and .squeezeAll;
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@terpstra terpstra terpstra approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

None yet
2 participants
@ingallsj @terpstra