forked from DikshaKapoor15/CA_assembler
-
Notifications
You must be signed in to change notification settings - Fork 0
/
pipe_with_data.py
833 lines (803 loc) · 42.2 KB
/
pipe_with_data.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
import os
f1=open("coded.mc")
lines=f1.readlines()
pc_dict={}
for line in lines:
[a1,a2]=line.split()
pc_dict[int(a1,16)]=a2
from registers import registers
from memory import memory
my_mem=memory()
my_reg=registers()
from my_memory import mem_from_data
for key in mem_from_data:
my_mem.write_byte(key,int(mem_from_data[key],2))
print(pc_dict)
class pipelining:
def __init__(self):
self.PC=0x0
self.IR=0
self.PC_temp=self.PC
self.clock=0
self.Cycles = 0
self.IF = '';
self.ID = {};
self.IE = {};
self.IM = [];
self.data = []
self.stall_one = False
self.stall_two = False
self.total_cycles = 0
def pipeline(self):
while(self.PC in pc_dict):
if(self.Cycles == 0):
self.fetch(pc_dict[self.PC])
self.Cycles+=1
self.total_cycles+=1
if(self.Cycles == 1):
print("-----------------------------------------------------------------------")
self.ID = self.decode(self.IF)
self.data.append(self.ID['operands'][len(self.ID['operands'])-1])
self.fetch(pc_dict[self.PC])
self.Cycles+=1
self.total_cycles+=1
if(self.Cycles == 2):
print("-----------------------------------------------------------------------")
if(self.ID['Format']=='R'):
self.IE = self.executeR(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'I'):
self.IE = self.executeI(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IL'):
self.IE = self.executeIL(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IJ'):
self.IE = self.executeIJ(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IS'):
self.IE = self.executeIS(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'SB'):
self.IE = self.executeSB(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'U'):
self.IE = self.executeU(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
print(self.IE)
if(self.ID['Format'] == 'UJ'):
self.IE = self.executeUj(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
self.ID = self.decode(self.IF)
self.data.append(self.ID['operands'][len(self.ID['operands'])-1])
self.fetch(pc_dict[self.PC])
self.Cycles+=1
self.total_cycles+=1
if(self.Cycles == 3):
print("-----------------------------------------------------------------------")
print(self.IE)
self.IM = self.IE['RegUpdate']
if(self.IE['MemWrite'][0]):
if(self.IE['MemWrite'][1]=='w'):
if(self.IE['MemWrite'][4]=='byte'):
my_mem.write_byte(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='word'):
my_mem.write_word(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='half'):
my_mem.write_half(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
else:
if(self.IE['MemWrite'][3]=='byte'):
retu = my_mem.ret_byte(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='word'):
retu = my_mem.ret_word(self.IE['MemWrite'][2])
print(len(self.IM))
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='half'):
retu = my_mem.ret_half(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
print("MEMORY ACCESSED")
for op in self.ID['operands'][:len(self.ID['operands'])-1]:
if (op == self.data[len(self.data)-2]):
self.stall_one = True
if(not self.stall_one):
if(self.ID['Format']=='R'):
self.IE = self.executeR(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'I'):
self.IE = self.executeI(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IL'):
self.IE = self.executeIL(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IJ'):
self.IE = self.executeIJ(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IS'):
self.IE = self.executeIS(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'SB'):
self.IE = self.executeSB(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'U'):
self.IE = self.executeU(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
print(self.IE)
if(self.ID['Format'] == 'UJ'):
self.IE = self.executeUj(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
if(self.stall_one or self.stall_two):
self.Cycles+=1
self.total_cycles+=1
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
print("----------Stalling the pipeline due to data dependency-----------")
self.Cycles+=1
self.total_cycles+=1
return
self.ID = self.decode(self.IF)
self.data.append(self.ID['operands'][len(self.ID['operands'])-1])
self.fetch(pc_dict[self.PC])
self.Cycles+=1
self.total_cycles+=1
if(self.Cycles >= 4):
print("-----------------------------------------------------------------------")
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
self.IM = self.IE['RegUpdate']
if(self.IE['MemWrite'][0]):
if(self.IE['MemWrite'][1]=='w'):
if(self.IE['MemWrite'][4]=='byte'):
my_mem.write_byte(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='word'):
my_mem.write_word(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='half'):
my_mem.write_half(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
else:
if(self.IE['MemWrite'][3]=='byte'):
retu = my_mem.ret_byte(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='word'):
retu = my_mem.ret_word(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='half'):
retu = my_mem.ret_half(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
print("MEMORY ACCESSED")
for op in self.ID['operands'][:len(self.ID['operands'])-1]:
if (op == self.data[len(self.data)-2]):
self.stall_one = True
if(op == self.data[len(self.data)-3]):
self.stall_two = True
if(self.stall_one or self.stall_two):
self.Cycles+=1
self.total_cycles+=1
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
print("----------Stalling the pipeline due to data dependency-----------")
self.Cycles+=1
self.total_cycles+=1
return
if(self.ID['Format']=='R'):
self.IE = self.executeR(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'I'):
self.IE = self.executeI(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IL'):
self.IE = self.executeIL(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IJ'):
self.IE = self.executeIJ(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IS'):
self.IE = self.executeIS(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'SB'):
self.IE = self.executeSB(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'U'):
self.IE = self.executeU(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
print(self.IE)
if(self.ID['Format'] == 'UJ'):
self.IE = self.executeUj(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
self.ID = self.decode(self.IF)
self.data.append(self.ID['operands'][len(self.ID['operands'])-1])
self.fetch(pc_dict[self.PC])
self.Cycles+=1
self.total_cycles+=1
print("-----------------------------------------------------------------------")
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
self.IM = self.IE['RegUpdate']
if(self.IE['MemWrite'][0]):
if(self.IE['MemWrite'][1]=='w'):
if(self.IE['MemWrite'][4]=='byte'):
my_mem.write_byte(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='word'):
my_mem.write_word(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='half'):
my_mem.write_half(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
else:
if(self.IE['MemWrite'][3]=='byte'):
retu = my_mem.ret_byte(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='word'):
retu = my_mem.ret_word(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='half'):
retu = my_mem.ret_half(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
print("MEMORY ACCESSED")
for op in self.ID['operands'][:len(self.ID['operands'])-1]:
if (len(self.data)>2 and op == self.data[len(self.data)-2]):
self.stall_one = True
elif(len(self.data)>3 and op == self.data[len(self.data)-3]):
self.stall_two = True
if(self.stall_one or self.stall_two):
self.Cycles+=1
self.total_cycles+=1
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
print("----------Stalling the pipeline due to data dependency-----------")
self.Cycles+=1
self.total_cycles+=1
return
if(self.ID['Format']=='R'):
self.IE = self.executeR(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'I'):
self.IE = self.executeI(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IL'):
self.IE = self.executeIL(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IJ'):
self.IE = self.executeIJ(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IS'):
self.IE = self.executeIS(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'SB'):
self.IE = self.executeSB(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'U'):
self.IE = self.executeU(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
print(self.IE)
if(self.ID['Format'] == 'UJ'):
self.IE = self.executeUj(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
self.ID = self.decode(self.IF)
self.data.append(self.ID['operands'][len(self.ID['operands'])-1])
self.Cycles+=1
self.total_cycles+=1
print("-----------------------------------------------------------------------")
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
self.IM = self.IE['RegUpdate']
if(self.IE['MemWrite'][0]):
if(self.IE['MemWrite'][1]=='w'):
if(self.IE['MemWrite'][4]=='byte'):
my_mem.write_byte(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='word'):
my_mem.write_word(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='half'):
my_mem.write_half(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
else:
if(self.IE['MemWrite'][3]=='byte'):
retu = my_mem.ret_byte(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='word'):
retu = my_mem.ret_word(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='half'):
retu = my_mem.ret_half(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
print("MEMORY ACCESSED")
for op in self.ID['operands'][:len(self.ID['operands'])-1]:
if (len(self.data)>2 and op == self.data[len(self.data)-2]):
self.stall_one = True
elif(len(self.data)>3 and op == self.data[len(self.data)-3]):
self.stall_two = True
if(self.stall_one or self.stall_two):
self.Cycles+=1
self.total_cycles+=1
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
print("----------Stalling the pipeline due to data dependency-----------")
self.Cycles+=1
self.total_cycles+=1
return
if(self.ID['Format']=='R'):
self.IE = self.executeR(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'I'):
self.IE = self.executeI(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IL'):
self.IE = self.executeIL(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IJ'):
self.IE = self.executeIJ(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'IS'):
self.IE = self.executeIS(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'SB'):
self.IE = self.executeSB(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1],self.ID['operands'][2])
if(self.ID['Format'] == 'U'):
self.IE = self.executeU(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
print(self.IE)
if(self.ID['Format'] == 'UJ'):
self.IE = self.executeUj(self.ID['Instruction'],self.ID['operands'][0],self.ID['operands'][1])
self.Cycles+=1
self.total_cycles+=1
print("-----------------------------------------------------------------------")
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
self.IM = self.IE['RegUpdate']
if(self.IE['MemWrite'][0]):
if(self.IE['MemWrite'][1]=='w'):
if(self.IE['MemWrite'][4]=='byte'):
my_mem.write_byte(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='word'):
my_mem.write_word(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
if(self.IE['MemWrite'][4]=='half'):
my_mem.write_half(self.IE['MemWrite'][2],self.IE['MemWrite'][3])
else:
if(self.IE['MemWrite'][3]=='byte'):
retu = my_mem.ret_byte(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='word'):
retu = my_mem.ret_word(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
if(self.IE['MemWrite'][3]=='half'):
retu = my_mem.ret_half(self.IE['MemWrite'][2])
self.IM.append(int(retu,2))
print("MEMORY ACCESSED")
self.Cycles+=1
self.total_cycles+=1
print("-----------------------------------------------------------------------")
if(self.IM[0]):
my_reg.write_reg(self.IM[1],self.IM[2])
print("REGISTER UPDATED")
self.Cycles+=1
self.total_cycles+=1
def fetch(self,mc_code):
self.IF=mc_code
self.PC_temp=self.PC
self.PC+=4
print("FETCH:Fetch instruction "+self.IF+" from address "+str(self.PC-4))
def decode(self,Ins):
out={}
curr_bin_ins=bin(int(Ins[2:],16))[2:].zfill(32)
opcode=curr_bin_ins[25:32]
if(opcode=="0110011"):
fun7=curr_bin_ins[0:7]
fun3=curr_bin_ins[17:20]
rs2=curr_bin_ins[7:12]
rs1=curr_bin_ins[12:17]
rd=curr_bin_ins[20:25]
if(fun7=="0100000"):
if(fun3=="000"):
print("DECODE: Operation is SUB, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'SUB'
out['operands'] = [rs1,rs2,rd]
return out
else:
print("DECODE: Operation is SRA, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'SRA'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun7=="0000001"):
if(fun3=="000"):
print("DECODE: Operation is MUL, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'MUL'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="100"):
print("DECODE: Operation is DIV, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'DIV'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="110"):
print("DECODE: Operation is REM, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'REM'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun7=="0000000"):
if(fun3=="000"):
print("DECODE: Operation is ADD, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'ADD'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="110"):
print("DECODE: Operation is OR, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'OR'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="101"):
print("DECODE: Operation is SRL, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'SRL'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="100"):
print("DECODE: Operation is XOR, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'XOR'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="111"):
print("DECODE: Operation is AND, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'AND'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="001"):
print("DECODE: Operation is SLL, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'SLL'
out['operands'] = [rs1,rs2,rd]
return out
elif(fun3=="010"):
print("DECODE: Operation is SLT, first operand R",int(rs1,2), " , Second operand R",int(rs2,2),", destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Format'] = 'R'
out['Instruction'] = 'SLT'
out['operands'] = [rs1,rs2,rd]
return out
elif(opcode=="0010011"):
fun3=curr_bin_ins[17:20]
rs1=curr_bin_ins[12:17]
rd=curr_bin_ins[20:25]
imm=curr_bin_ins[0:12]
if(fun3=="000"):
print("DECODE: Operation is ADDI, first operand R",int(rs1,2), " , Second operand is Immediate field,destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2))
out['Format'] = 'I'
out['Instruction'] = 'ADDI'
out['operands'] = [rs1,imm,rd]
return out
if(fun3=="111"):
print("DECODE: Operation is ANDI, first operand R",int(rs1,2), " , Second operand is Immediate field,destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2))
out['Format'] = 'I'
out['Instruction'] = 'ANDI'
out['operands'] = [rs1,imm,rd]
if(fun3=="110"):
print("DECODE: Operation is ORI, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2))
out['Format'] = 'I'
out['Instruction'] = 'ORI'
out['operands'] = [rs1,imm,rd]
elif(opcode=="0000011"):
fun3=curr_bin_ins[17:20]
rs1=curr_bin_ins[12:17]
rd=curr_bin_ins[20:25]
imm=curr_bin_ins[0:12]
out['Format'] = 'IL'
out['operands'] = [rs1,imm,rd]
if(fun3=="000"):
print("DECODE: Operation is LB, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'LB'
# elif(fun3=="011"):
# print("DECODE: Operation is LD, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
# print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
# out['Instruction'] = 'LD'
elif(fun3=="001"):
print("DECODE: Operation is LH, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'LH'
elif(fun3=="010"):
print("DECODE: Operation is LW, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'LW'
elif(opcode=="1100111"):
fun3=curr_bin_ins[17:20]
rs1=curr_bin_ins[12:17]
rd=curr_bin_ins[20:25]
imm=curr_bin_ins[0:12]
if(fun3=="000"):
print("DECODE: Operation is JALR, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2))
out['Format'] = 'IJ'
out['Instruction'] = 'JALR'
out['operands'] = [rs1,imm,rd]
elif(opcode=="0100011"):
fun3=curr_bin_ins[17:20]
rs1=curr_bin_ins[12:17]
rd=curr_bin_ins[7:12]
imm=curr_bin_ins[0:7]+curr_bin_ins[20:25]
out['Format'] = 'IS'
out['operands'] = [rs1,imm,rd]
if(fun3=="010"):
print("DECODE: Operation is SW, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'SW'
# elif(fun3=="011"):
# print("DECODE: Operation is SD, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
# print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
# out['Instruction'] = 'SD'
elif(fun3=="000"):
print("DECODE: Operation is SB, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'SB'
elif(fun3=="001"):
print("DECODE: Operation is SH, first operand R",int(rs1,2), " , Second operand is Immediate field, destination register R",int(rd,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", The immediate value is ",int(imm,2) )
out['Instruction'] = 'SH'
elif(opcode=="1100011"):
fun3=curr_bin_ins[17:20]
rs1=curr_bin_ins[12:17]
rs2=curr_bin_ins[7:12]
imm=curr_bin_ins[0:7]+curr_bin_ins[20:25]
out['Format'] = 'SB'
out['operands'] = [rs1,imm,rs2]
if(fun3=="000"):
print("DECODE: Operation is BEQ, first operand R",int(rs1,2), " , second operand R",int(rs2,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", Second register R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Instruction'] = 'BEQ'
if(fun3=="001"):
print("DECODE: Operation is BNE, first operand R",int(rs1,2), " , second operand R",int(rs2,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", Second register R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Instruction'] = 'BNE'
if(fun3=="100"):
print("DECODE: Operation is BLT, first operand R",int(rs1,2), " , second operand R",int(rs2,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", Second register R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Instruction'] = 'BLT'
if(fun3=="101"):
print("DECODE: Operation is BGE, first operand R",int(rs1,2), " , second operand R",int(rs2,2))
print("DECODE: Read registers R",int(rs1,2)," = ",my_reg.regVal(int(rs1,2)),", Second register R",int(rs2,2)," = ",my_reg.regVal(int(rs2,2)))
out['Instruction'] = 'BGE'
elif(opcode=="0010111" or opcode=="0110111"):
rd=curr_bin_ins[20:25]
imm=curr_bin_ins[0:20]
if(opcode=="0110111"):
print("DECODE: Operation is LUI, first operand is Immediate field, destination register R",int(rd,2))
print("DECODE: The immediate value is",int(imm,2))
out['Format'] = 'U'
out['Instruction'] = 'LUI'
out['operands'] = [imm,rd]
elif(opcode=="0010111"):
print("DECODE: Operation is AUIPC, first operand is Immediate field, destination register R",int(rd,2))
print("DECODE: The immediate value is",int(imm,2))
out['Format'] = 'U'
out['Instruction'] = 'AUIPC'
out['operands'] = [imm,rd]
elif(opcode=="1101111"):
rd=curr_bin_ins[20:25]
imm=curr_bin_ins[0:20]
# print(imm)
imm0=imm[0]
imm1=imm[1:12]
imm2=imm[12]
imm3=imm[13:20]
imm_=imm0+imm3+imm2+imm1
# print(imm_)
print("DECODE: Operation is JAL,the first operand is Immediate field, destination register R",int(rd,2))
print("DECODE: The immediate value is",int(imm_,2))
out['Format'] = 'UJ'
out['Instruction'] = 'JAL'
out['operands'] = [imm_,rd]
return out
def executeUj(self,func,im,r):
out = {}
if(im[0]=='1'):
val=-2**20+int(im,2)-1
else:
val=int(im,2)
out['MemWrite']= [False]
out['RegUpdate']=[True]
out['RegUpdate']+=[int(r,2),self.PC]
self.PC=self.PC_temp+val
print("EXECUTED")
return out
def executeR(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [False]
out['RegUpdate'] = [True]
if(func=="ADD"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1+num2]
print("EXECUTED")
return out
if(func=="SUB"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1-num2]
print("EXECUTED")
return out
if(func=="MUL"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1*num2]
print("EXECUTED")
return out
if(func=="DIV"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1/num2]
print("EXECUTED")
return out
if(func=="SRA"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
xx=bin(num1)[2:]
my_msb=xx[31]
aa=str(num1>>num2)
aa[0:num2]=my_msb
out['RegUpdate']+=[int(r3,2),int(aa,2)]
print("EXECUTED")
return out
if(func=="SRL"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1>>num2]
print("EXECUTED")
return out
if(func=="AND"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1&num2]
print("EXECUTED")
return out
if(func=="XOR"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1^num2]
print("EXECUTED")
return out
if(func=="REM"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1%num2]
print("EXECUTED")
return out
if(func=="SLT"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
if(num1>num2):
out['RegUpdate']+=[int(r3,2),0]
print("EXECUTED")
return out
else:
out['RegUpdate']+=[int(r3,2),1]
print("EXECUTED")
return out
if(func=="SLL"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1<<num2]
print("EXECUTED")
return out
if(func=="OR"):
num1=my_reg.regVal(int(r1,2))
num2=my_reg.regVal(int(r2,2))
out['RegUpdate']+=[int(r3,2),num1|num2]
print("EXECUTED")
return out
def executeI(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [False]
out['RegUpdate'] = [True]
if(func=="ADDI"):
num1=my_reg.regVal(int(r1,2))
num2=int(r2,2)
if(r2[0]=='1'):
num2=-2**12+num2
out['RegUpdate']+=[int(r3,2),num1+num2]
if(func=="ANDI"):
num1=my_reg.regVal(int(r1,2))
num2=int(r2,2)
if(r2[0]=='1'):
num2=-2**12+num2
out['RegUpdate']+=[int(r3,2),num1&num2]
if(func=="ORI"):
num1=my_reg.regVal(int(r1,2))
num2=int(r2,2)
if(r2[0]=='1'):
num2=-2**12+num2
out['RegUpdate']+=[int(r3,2),num1|num2]
print("EXECUTED")
return out
def executeU(self,func,im,r):
out={}
out['MemWrite'] = [False]
out['RegUpdate'] = [True]
if(func=="LUI"):
im=im+"000000000000"
im=int(im,2)
out['RegUpdate']+=[int(r,2),im]
else:
im=im+"000000000000"
im=int(im,2)
im=im+self.PC_temp
out['RegUpdate']+=[int(r,2),im]
print("EXECUTED")
return out
def executeIS(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [True]
out['RegUpdate'] = [False]
if(r2[0]=='1'):
eff_address=my_reg.regVal(int(r1,2))-2**12+int(r2,2)
else:
eff_address=my_reg.regVal(int(r1,2))+int(r2,2)
if(func=="SB"):
out['MemWrite']+=['w',eff_address,my_reg.regVal(int(r3,2)),'byte']
elif(func=="SH"):
out['MemWrite']+=['w',eff_address,my_reg.regVal(int(r3,2)),'half']
elif(func=="SW"):
out['MemWrite']+=['w',eff_address,my_reg.regVal(int(r3,2)),'word']
print("EXECUTED")
return out
def executeSB(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [False]
out['RegUpdate'] = [False]
if(r2[0]=='1'):
val=-2**12+int(r2,2)-1
else:
val=int(r2,2)
if(func=="BEQ"):
if(my_reg.regVal(int(r1,2))==my_reg.regVal(int(r3,2))):
self.PC=self.PC_temp+val
elif(func=="BNE"):
if(my_reg.regVal(int(r1,2))!=my_reg.regVal(int(r3,2))):
self.PC=self.PC_temp+val
elif(func=="BLT"):
if(my_reg.regVal(int(r1,2))<my_reg.regVal(int(r3,2))):
self.PC=self.PC_temp+val
elif(func=="BGE"):
if(my_reg.regVal(int(r1,2))>=my_reg.regVal(int(r3,2))):
self.PC=self.PC_temp+val
print("EXECUTED")
return out
def executeIL(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [True]
out['RegUpdate'] = [True]
if(r2[0]=='1'):
eff_address=my_reg.regVal(int(r1,2))-2**12+int(r2,2)
else:
eff_address=my_reg.regVal(int(r1,2))+int(r2,2)
if(func=="LB"):
out['MemWrite']+=['r',eff_address,'byte']
out['RegUpdate']+=[int(r3,2)]
if(func=="LH"):
out['MemWrite']+=['r',eff_address,'half']
out['RegUpdate']+=[int(r3,2)]
if(func=="LW"):
out['MemWrite']+=['r',eff_address,'word']
out['RegUpdate']+=[int(r3,2)]
print("EXECUTED")
return out
def executeIJ(self,func,r1,r2,r3):
out={}
out['MemWrite'] = [False]
out['RegUpdate'] = [True]
if(r2[0]=='1'):
eff_address=my_reg.regVal(int(r1,2))-2**12+int(r2,2)
else:
eff_address=my_reg.regVal(int(r1,2))+int(r2,2)
out['RegUpdate'].append(int(r3,2))
out['RegUpdate'].append(self.PC)
self.PC=eff_address
print("EXECUTED")
return out
my_pipeline = pipelining()
while(1):
my_pipeline.pipeline()
if(my_pipeline.stall_one or my_pipeline.stall_two):
my_pipeline.stall_one = False
my_pipeline.stall_two = False
my_pipeline.data = []
my_pipeline.Cycles = 2
else:
break
print("--------------------------------------------------------------")
print("NO. of Cycles: ",my_pipeline.total_cycles)
print("------------------Registers------------------------------\n\n")
mr=my_reg.ret_reg()
for i in range(0,32):
print("x"+str(i)+":"+str(mr[i]))
print("\n")
pr=my_mem.returnAll()
print("--------------------Memory-------------------------------\n\n")
for key in pr:
print(hex(key),":"+pr[key]+"\n")