Generate diagrams based on SpinalHDL code #105
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10 warnings
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L71
+ parentList.nonEmpty && parentList.size > 1 && parentList.last.getClass.getSimpleName == "" && !parentList.last
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L71
+ .isInstanceOf[Data]
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L81
+class ModuleDataStructure(module: Component, clkMap: mutable.HashMap[ClockDomain, Int]) {
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L106
+class GenNodesAndEdges(module: Component, moduleName: String, clkMap: mutable.HashMap[ClockDomain, Int]) {
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L119
+ private val systemRegisters = moduleAnalyze.getNets(net =>
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fmt-lint:
lib/src/main/scala/spinal/lib/tools/HDElkDiagramGen.scala#L120
+ net.getComponent().getName() == module.getName() && !topInOuts.contains(net) && !allRegisters.contains(net)
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