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SpinalHDL 1.10.1
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Merge remote-tracking branch 'origin/dev'

# Conflicts:
#	project/Version.sc
#	project/Version.sc~HEAD
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Dolu1990 committed Feb 1, 2024
2 parents 19725a4 + a648c10 commit 2527c7c
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1 change: 1 addition & 0 deletions .mill-version
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
0.11.6
51 changes: 29 additions & 22 deletions build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,17 @@ import mill._, scalalib._, publish._
import $file.project.Version

trait SpinalModule extends SbtModule { outer =>
def scalaVersion = Version.SpinalVersion.compilers(0)
def scalatestVersion = "3.2.14"
def scalacOptions = super.scalacOptions() ++ Seq("-unchecked", "-target:jvm-1.8")
def javacOptions = super.javacOptions() ++ Seq("-source", "1.8", "-target", "1.8")

val IvyDeps = Agg(
ivy"org.scala-lang:scala-library:${scalaVersion}",
ivy"net.java.dev.jna:jna:5.5.0",
ivy"net.java.dev.jna:jna-platform:5.5.0",
ivy"org.slf4j:slf4j-api:1.7.25",
ivy"org.scala-lang.modules::scala-xml:1.2.0"
ivy"org.scalactic:scalactic::3.2.10",
ivy"net.java.dev.jna:jna:5.12.1",
ivy"net.java.dev.jna:jna-platform:5.12.1",
ivy"org.slf4j:slf4j-api:2.0.5",
ivy"org.scala-lang.modules::scala-xml:1.3.0"
)
}

Expand All @@ -32,36 +33,40 @@ trait SpinalPublishModule extends PublishModule {
)
}

object idslpayload extends SpinalModule with SpinalPublishModule {
object idslpayload extends Cross[IdslPayload](Version.SpinalVersion.compilers)
trait IdslPayload extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.idslpayload")
override def artifactName = "spinalhdl-idsl-payload"
def ivyDeps = super.ivyDeps() ++ Agg(ivy"org.scala-lang:scala-reflect:${scalaVersion}")
}

object idslplugin extends SpinalModule with SpinalPublishModule {
object idslplugin extends Cross[IdslPlugin](Version.SpinalVersion.compilers)
trait IdslPlugin extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.idslplugin")
override def artifactName = "spinalhdl-idsl-plugin"
def moduleDeps = Seq(idslpayload)
def moduleDeps = Seq(idslpayload(crossScalaVersion))
def ivyDeps = super.ivyDeps() ++ Agg(ivy"org.scala-lang:scala-compiler:${scalaVersion}")
def pluginOptions = T { Seq(s"-Xplugin:${assembly().path}") }
}

object sim extends SpinalModule with SpinalPublishModule {
object sim extends Cross[Sim](Version.SpinalVersion.compilers)
trait Sim extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.sim")
def ivyDeps = super.ivyDeps() ++ Agg(
ivy"commons-io:commons-io:2.4",
ivy"commons-io:commons-io:2.11.0",
ivy"net.openhft:affinity:3.21ea1.1",
ivy"org.slf4j:slf4j-simple:1.7.25",
ivy"com.github.oshi:oshi-core:5.2.0"
)
def publishVersion = Version.SpinalVersion.sim
}

object lib extends SpinalModule with SpinalPublishModule {
object lib extends Cross[Lib](Version.SpinalVersion.compilers)
trait Lib extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.lib")
def moduleDeps = Seq(core, sim)
def scalacOptions = super.scalacOptions() ++ idslplugin.pluginOptions()
def ivyDeps = super.ivyDeps() ++ Agg(ivy"commons-io:commons-io:2.4", ivy"org.scalatest::scalatest:3.2.5")
def moduleDeps = Seq(core(crossScalaVersion), sim(crossScalaVersion))
def scalacOptions = super.scalacOptions() ++ idslplugin(crossScalaVersion).pluginOptions()
def ivyDeps = super.ivyDeps() ++ Agg(ivy"commons-io:commons-io:2.11.0", ivy"org.scalatest::scalatest:${scalatestVersion}")
def publishVersion = Version.SpinalVersion.lib
}

Expand All @@ -72,11 +77,12 @@ def gitHash(dir: os.Path) = (try {
case e: java.io.IOException => "???"
}).linesIterator.next()

object core extends SpinalModule with SpinalPublishModule {
object core extends Cross[Core](Version.SpinalVersion.compilers)
trait Core extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.core")
def moduleDeps = Seq(idslplugin, sim)
def moduleDeps = Seq(idslplugin(crossScalaVersion), sim(crossScalaVersion))

def scalacOptions = super.scalacOptions() ++ idslplugin.pluginOptions()
def scalacOptions = super.scalacOptions() ++ idslplugin(crossScalaVersion).pluginOptions()
def ivyDeps = super.ivyDeps() ++ Agg(
ivy"org.scala-lang:scala-reflect:${scalaVersion}",
ivy"com.github.scopt::scopt:3.7.1",
Expand All @@ -98,13 +104,14 @@ object core extends SpinalModule with SpinalPublishModule {
}
}

object tester extends SpinalModule with SpinalPublishModule {
object tester extends Cross[Tester](Version.SpinalVersion.compilers)
trait Tester extends SpinalModule with SpinalPublishModule with CrossSbtModule {
def mainClass = Some("spinal.tester")
def moduleDeps = Seq(core, sim, lib)
def moduleDeps = Seq(core(crossScalaVersion), sim(crossScalaVersion), lib(crossScalaVersion))
def scalacOptions = super.scalacOptions()
def ivyDeps = super.ivyDeps() ++ Agg(ivy"org.scalatest::scalatest:3.2.5")
def ivyDeps = super.ivyDeps() ++ Agg(ivy"org.scalatest::scalatest:${scalatestVersion}")

object test extends Tests with TestModule.ScalaTest {
def ivyDeps = Agg(ivy"org.scalatest::scalatest::3.2.5")
object test extends CrossSbtModuleTests with TestModule.ScalaTest {
def ivyDeps = Agg(ivy"org.scalatest::scalatest::${scalatestVersion}")
}
}
6 changes: 6 additions & 0 deletions core/src/main/scala/spinal/core/Data.scala
Original file line number Diff line number Diff line change
Expand Up @@ -318,6 +318,7 @@ trait Data extends ContextUser with NameableByComponent with Assignable with Spi

/** set a data as inout */
def asInOut(): this.type = {
assert(this.isAnalog, "inout can only be used on Analog signal")
if(this.component != Component.current) {
LocatedPendingError(s"You should not set $this as output outside its own component." )
}else {
Expand Down Expand Up @@ -346,6 +347,11 @@ trait Data extends ContextUser with NameableByComponent with Assignable with Spi

/** Set baseType to reg */
def setAsReg(): this.type
/** Recursively set baseType to reg only for output */
def setOutputAsReg(): this.type = {
flatten.filter(_.dir == out).foreach(_.setAsReg())
this
}
/** Set baseType to Combinatorial */
def setAsComb(): this.type

Expand Down
71 changes: 71 additions & 0 deletions core/src/main/scala/spinal/core/HardMap.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,71 @@
package spinal.core

import spinal.idslplugin.Location

import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer

object HardMap{
def apply(content : Seq[NamedType[_ <: Data]]) : HardMap = {
val ret = new HardMap()
content.foreach(e => ret.add(e))
ret
}
}

class HardMap extends MultiData {
val storage = mutable.LinkedHashMap[NamedType[Data], Data]()
var elementsCache : ArrayBuffer[(String, Data)] = null

def keyToName(key : Any) = key match {
case n: Nameable if n.isNamed => n.getName()
}

def update[T <: Data](key : NamedType[T], value : T): Unit = {
assert(elementsCache == null)
assert(!storage.contains(key.asInstanceOf[NamedType[Data]]))
storage(key.asInstanceOf[NamedType[Data]]) = value
if(OwnableRef.proposal(value, this)) value.setPartialName(keyToName(key), Nameable.DATAMODEL_WEAK)
}

def add[T <: Data](key: NamedType[T]) : Unit = {
this(key) = key()
}

def apply[T <: Data](key: NamedType[T]): T = {
storage(key.asInstanceOf[NamedType[Data]]).asInstanceOf[T]
}

override def elements: ArrayBuffer[(String, Data)] = {
if(elementsCache == null) {
elementsCache = ArrayBuffer[(String, Data)]()
for ((k, d) <- storage) {
val name = keyToName(k)
elementsCache += name -> d
}
}
elementsCache
}

def hardMapAssign(that: HardMap)(f: (Data, Data) => Unit): Unit = {
for ((name, element) <- elements) {
val other = that.find(name)
if (other == null) {
LocatedPendingError(s"Bundle assignment is not complete. $this need '$name' but $that doesn't provide it.")
}
else {
f(element, other)
}
}
}

protected override def assignFromImpl(that: AnyRef, target: AnyRef, kind: AnyRef)(implicit loc: Location): Unit = {
that match {
case that: HardMap =>
if (!this.getClass.isAssignableFrom(that.getClass)) SpinalError("HardMap must have the same final class to" +
" be assigned. Either use assignByName or assignSomeByName at \n" + ScalaLocated.long)
hardMapAssign(that)((to, from) => to.compositAssignFrom(from, to, kind))
case _ => throw new Exception("Undefined assignment")
}
}
}
15 changes: 9 additions & 6 deletions core/src/main/scala/spinal/core/Misc.scala
Original file line number Diff line number Diff line change
Expand Up @@ -617,13 +617,16 @@ object ContextSwapper{
case cu: ContextUser => cu.parentScope = topBody
case _ =>
}
topBody.head = addedHead
addedHead.lastScopeStatement = null.asInstanceOf[Statement]
addedLast.nextScopeStatement = oldHead
if(oldHead != null) oldHead.lastScopeStatement = addedLast
if(oldLast != null) oldLast.nextScopeStatement = null.asInstanceOf[Statement]
topBody.last = oldLast

if(addedHead != null) {
topBody.head = addedHead
addedHead.lastScopeStatement = null.asInstanceOf[Statement]
addedLast.nextScopeStatement = oldHead
if (oldHead != null) oldHead.lastScopeStatement = addedLast
if (oldLast != null) oldLast.nextScopeStatement = null.asInstanceOf[Statement]
topBody.last = oldLast
}

ret // return the value returned by that
}
}
Expand Down
6 changes: 3 additions & 3 deletions core/src/main/scala/spinal/core/Trait.scala
Original file line number Diff line number Diff line change
Expand Up @@ -937,13 +937,13 @@ trait Num[T <: Data] {
*/
trait BitwiseOp[T <: Data]{

/** Logical AND operator */
/** Bitwise AND operator */
def &(right: T): T

/** Logical OR operator */
/** Bitwise OR operator */
def |(right: T): T

/** Logical XOR operator */
/** Bitwise XOR operator */
def ^(right: T): T

/** Inverse bitwise operator */
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -598,8 +598,11 @@ class ComponentEmitterVerilog(

def emitEnumParams(): Unit = {
for((e,encoding) <- localEnums) {
for(element <- e.elements) {
localparams ++= s" localparam ${emitEnumLiteral(element, encoding,"")} = ${idToBits(element, encoding)};\n"
for (element <- e.elements) {
localparams ++= s" localparam ${emitEnumLiteral(element, encoding, "")} = ${idToBits(element, encoding)};\n"
}
if(encoding == binaryOneHot) for (element <- e.elements) {
localparams ++= s" localparam ${emitEnumLiteral(element, encoding, "")}_OH_ID = ${element.position};\n"
}
}
}
Expand Down Expand Up @@ -825,8 +828,13 @@ class ComponentEmitterVerilog(
def emitIsCond(that: Expression): String = {
that match {
case lit: EnumLiteral[_] if (lit.encoding == binaryOneHot) => {
val expr = emitEnumLiteral(lit.senum, lit.encoding)
s"(((${emitExpression(switchStatement.value)}) & ${expr}) == ${expr})"
switchValue match {
case _ : SpinalEnumCraft[_] => s"(${emitExpression(switchStatement.value)}[${emitEnumLiteral(lit.senum, lit.encoding)}_OH_ID])"
case _ => {
val expr = emitEnumLiteral(lit.senum, lit.encoding)
s"(((${emitExpression(switchStatement.value)}) & ${expr}) == ${expr})"
}
}
}
}
}
Expand Down Expand Up @@ -1562,8 +1570,8 @@ end
encoding match {
case `binaryOneHot` => {
(e.left, e.right) match {
// case (sig, lit : EnumLiteral[_]) => s"(${if (eguals) "" else "! "}${emitExpression(sig)}[${lit.senum.position}])"
// case (lit : EnumLiteral[_], sig) => s"(${if (eguals) "" else "! "}${emitExpression(sig)}[${lit.senum.position}])"
case (sig : SpinalEnumCraft[_], lit : EnumLiteral[_]) => s"(${if (eguals) "" else "! "}${emitExpression(sig)}[${emitEnumLiteral(lit.senum, lit.encoding)}_OH_ID])"
case (lit : EnumLiteral[_], sig : SpinalEnumCraft[_]) => s"(${if (eguals) "" else "! "}${emitExpression(sig)}[${emitEnumLiteral(lit.senum, lit.encoding)}_OH_ID])"
case _ => s"((${emitExpression(e.left)} & ${emitExpression(e.right)}) ${if (eguals) "!=" else "=="} ${encoding.getWidth(enumDef)}'b${"0" * encoding.getWidth(enumDef)})"
}
}
Expand Down
5 changes: 2 additions & 3 deletions core/src/main/scala/spinal/core/sim/SimBootstraps.scala
Original file line number Diff line number Diff line change
Expand Up @@ -454,13 +454,13 @@ object SpinalXSimBackend {
vconfig.xciSourcesPaths = xciSourcesPaths
vconfig.bdSourcesPaths = bdSourcesPaths
vconfig.toplevelName = rtl.toplevelName
vconfig.wavePath = "test.wdb"
vconfig.waveFormat = waveFormat match {
case WaveFormat.DEFAULT => WaveFormat.WDB
case _ => waveFormat
}
vconfig.workspaceName = workspaceName
vconfig.workspacePath = workspacePath
vconfig.wavePath = s"${workspacePath}/${workspaceName}/${rtl.toplevelName}.wdb"
vconfig.xilinxDevice = xilinxDevice
vconfig.userSimulationScript = simScript
vconfig.xelabFlags = simulatorFlags.toArray
Expand Down Expand Up @@ -519,7 +519,6 @@ class SimVerilatorPhase extends PhaseNetlist {
pc.walkDeclarations { d =>
d match {
case x: SpinalTagReady if (x.hasTag(SimPublic)) => {
x.removeTag(SimPublic)
x.addTag(Verilator.public)
}
case _ =>
Expand Down Expand Up @@ -684,7 +683,7 @@ case class SpinalSimConfig(
var _simScript : String = null,
var _timePrecision : TimeNumber = null,
var _timeScale : TimeNumber = null,
var _testPath : String = "$WORKSPACE/$COMPILED"
var _testPath : String = "$WORKSPACE/$COMPILED/$TEST"
){


Expand Down
5 changes: 3 additions & 2 deletions core/src/main/scala/spinal/core/sim/package.scala
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ import scala.collection.generic.Shrinkable
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
import scala.collection.Seq
import scala.util.Random

/**
* Simulation package
Expand Down Expand Up @@ -284,7 +285,7 @@ package object sim {


implicit class SimSeqPimper[T](pimped: Seq[T]){
def randomPick(): T = pimped(simRandom.nextInt(pimped.length))
def randomPick(rand : Random = simRandom): T = pimped(rand.nextInt(pimped.length))
def randomPickWithIndex(): (T, Int) = {
val index = simRandom.nextInt(pimped.length)
(pimped(index), index)
Expand Down Expand Up @@ -659,7 +660,7 @@ package object sim {

private def getBool(manager: SimManager, who: Bool): Bool = {
val component = who.component
if((who.isInput || who.isOutput) && component != null && component.parent == null){
if((who.isInput || who.isOutput) && component != null && component.parent == null || who.hasTag(SimPublic)){
who
}else {
manager.userData.asInstanceOf[Component].pulledDataCache.getOrElse(who, null).asInstanceOf[Bool]
Expand Down
11 changes: 9 additions & 2 deletions lib/src/main/scala/spinal/lib.scala
Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,8 @@ package object lib {
def toBinInts(num: Int): List[Int] = binarySystem.LiteralToBinInts.BigIntToBinInts(toBigInt, num)
def toDecInts(num: Int): List[Int] = binarySystem.LiteralToBinInts.BigIntToDecInts(toBigInt, num)
def toOctInts(num: Int): List[Int] = binarySystem.LiteralToBinInts.BigIntToOctInts(toBigInt, num)

def toBytes: List[Byte] = binarySystem.LiteralToBytes.bigIntToBytes(toBigInt)
}

implicit class BigIntRicher(value: BigInt) extends LiteralRicher {
Expand All @@ -139,6 +141,11 @@ package object lib {
override val defaultAlignBit: Int = 8
}

implicit class BytesRicher(lb: List[Byte]) {
def bytesToHex: String = binarySystem.BytesToLiteral.bytesToHexString(lb)
def bytesToBigInt: BigInt = binarySystem.BytesToLiteral.bytesToBigInt(lb)
}

implicit class BinIntsRicher(li: List[Int]){
def binIntsToOctAlignHigh: String = binarySystem.BinIntsToLiteral.binIntsToOctString(li, true)
def binIntsToHexAlignHigh: String = binarySystem.BinIntsToLiteral.binIntsToHexString(li, true)
Expand All @@ -148,7 +155,7 @@ package object lib {
def binIntsToInt: Int = binIntsToBigInt.toInt
def binIntsToLong: Long = binIntsToBigInt.toLong
}


val OHMux = new MuxOHImpl
}

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