About IOBUF usage #1277
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I want to use package limit
import spinal.core._
import spinal.lib._
import spinal.lib.blackbox.xilinx.s7._
object IOBUFtestGen extends App {
case class IOBUFtest() extends Component {
val io = new Bundle {
val i = in(Bool)
val t = in(Bool)
val o = out(Bool)
val io = inout(Bool)
}
val buf = IOBUF()
buf.I := io.i
buf.T := io.t
io.o := buf.O
io.io := buf.IO
}
SpinalConfig().generateVerilog(IOBUFtest())
} However, I got some errors.
I try to comment these lines of case class IOBUF() extends BlackBox {
val I, T = in Bool ()
val O = out Bool ()
val IO = inout(Analog(Bool()))
// when(T){
// IO := I
// }
// O := IO
} Is there another solution. Thanks a lot! |
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Replies: 4 comments 5 replies
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Hi, I think the issue is that your toplevel val io = inout(Bool) should be val io = inout(Analog(Bool)) On upstream i will add some code to catch this. |
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I think you need to update SpinalHDL, 1.10.0 should work fine with it. |
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I updated SpinalHDL to 1.10.0, and it worked. |
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I got another issue after updating to 1.10.0. case class RealData(
axiconf: Axi4Config,
bramconf: BRAMConfig,
memDepth: Int
) extends Component {
val io = new Bundle {
val s_axi = slave(Axi4(axiconf))
val s_bram = slave(BRAM(bramconf))
val bram_clk = in(Bool)
val bram_clk_rstn = in(Bool)
}
val axi_bus = Axi4SlaveFactory(io.s_axi)
val mem = Mem(Bits(axiconf.dataWidth bit), memDepth)
val bram_domain = new ClockDomain(
clock = io.bram_clk,
reset = io.bram_clk_rstn,
config = ClockDomainConfig(
clockEdge = RISING,
resetKind = SYNC,
resetActiveLevel = LOW
)
)
require(bramconf.dataWidth <= mem.width)
require(
(mem.width / bramconf.dataWidth) > 0 && (((mem.width / bramconf.dataWidth) & (mem.width / bramconf.dataWidth - 1)) == 0)
)
var multiple = mem.width / bramconf.dataWidth
axi_bus.readSyncMemMultiWord(mem, 0)
val bram_area = new ClockingArea(bram_domain) {
val memaddr = (io.s_bram.addr >> log2Up(mem.width / 8)).resize(log2Up(memDepth))
// mask offset
val memoffset = ((io.s_bram.addr >> log2Up(bramconf.dataWidth / 8)) & (multiple - 1))
.resize(log2Up(multiple)) << log2Up(bramconf.dataWidth / 8)
// data left shift
val memlshift = ((io.s_bram.addr >> log2Up(bramconf.dataWidth / 8)) & (multiple - 1))
.resize(log2Up(multiple)) << log2Up(bramconf.dataWidth)
val memmask = (io.s_bram.we.resize(mem.width / 8) |<< memoffset)
val memdata = (io.s_bram.wrdata.resize(mem.width) |<< memlshift)
mem.write(memaddr, memdata, io.s_bram.en, memmask)
io.s_bram.rddata := 0
}
} Error |
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I think you need to update SpinalHDL, 1.10.0 should work fine with it.