Online SpinalHDL webinar December 16 2022

[Dolu1990]

Hi,

With Nicolas we are looking to organize a online SpinalHDL webinar.
The idea would be to have presentations made by the community / you to present something around SpinalHDL (project / API / dev / ...).
The date would be December 16 between 10am to 2pm CET.
Let's me know if you are interrested / would have a presentations / what you would like to present ^^

Deadline to propose a talk : last day of November :)

[saahm]

Hey,
I would be able to present my work in which I use SpinalHDL to do some research and education. SpinalHDL is mostly used as tool in my daily work so I dont have to write tedious Verilog or VHDL. It also neatly gives me access to use Verilator as a simulator and makes my life generally easier.
I always get enthusiastic myself when I tell people why SpinalHDL should be used and try to promote this in my research work too.

I guess you want to collect enough people actively participating before having some idea about length per talk and such.
So this way I leave the note that I'm interested to contribute as a speaker.

[Dolu1990]

So currently we were thinking about 45 minutes talks, but i think it can be a "up to 45 mn".

I think the most important is to not try to extend a presentation to make it fill a given timing ^^

[saahm]

Makes sense to me, I'd also not wanna strech things if people know a bit of SpinalHDL anyway.

[sebastien-riou]

I would like to present our use of SpinalHDL, VexRISCV and SaxonSoc at Tiempo-Secure.

[Dolu1990]

Cool :)

[Dolu1990]

I'm thinking about presenting NaxRiscv's SpinalHDL side

[Dolu1990]

Note, can also be mixed presentation / live demo

[Readon]

I would like to present some progress of formal verification facilities in SpinalHDL lib.

[Dolu1990]

@Readon @saahm @sebastien-riou @Dolu1990
I think we should provide the following info :

• Title
• Little abstract
• Estimated duration the talk

[SandmanDZ]

Can the potential presenters who are interested to share in this virtual summit update their title/abstract/duration here so that I can help make a poster and spread the word around~

[distributed]

Here's my contribution.

Title: Coding a microprogrammed protocol receiver in SpinalHDL

Abstract: We present a microcode-like approach to coding a communications protocol receiver used in flying, handheld and stationary 3D scanners. Decoding the protocol in random logic leads to unattractively high resource usage. Therefore, a microprogrammed approach was chosen where data out of preprogrammed memories controls the rather regularly organized data path. The talk will highlight the construction of the microinstructions and their physical representation, showing how code evaluated at Scala runtime can be elegantly intertwined with Spinal code representing hardware.

Duration: 25 minutes

[Readon]

Title:
Recent progress on formal verification support on SpinalHDL

Little abstract:
The formal verification is a technology to verify design, which helps to find the corner cases. SpinalHDL have provided an integration of this tech with SymbiYosys easily. The brief introduction on how to verify a design would be presented by example. Some new build blocks helping to simplify the verification process would be introduced. At last, a short overview of the verification of some facilities in SpinalHDL's lib would also be summarized.

Estimated duration of the talk: 15 mins

[Jeff-Ciesielski]

Title: Utilizing SpinalHDL to Accelerate Neuroscience

Abstract: This presentation will cover how LeafLabs leverages SpinalHDL to enable the rapid development of a devices used for Neuroscience research ranging from mixed-signal Electrophysiology ASICs to FPGA based designs for system control and USB3 connectivity.

Estimated duration of the talk: 15 mins

[sebastien-riou]

Title: SpinalHDL for ASIC

Abstract: Highlights of a ASIC done entirely in SpinalHDL, fabricated in GF22FDX. Focus on pads, RAMs and FPGA for ASIC verification.

Estimated duration of the talk: 20 mins

[teilraum]

Title: A Network Attached Deep Learning Accelerator​ for FPGA Clusters

Abstract:
We present a Layer parallel framework for DNN training on an FPGA cluster.
All hardware description is done using SpinalHDL.
We will give an overview of our approach and some examples where SpinalHDL came in handy.

Estimated duration of the talk: 20 mins

[Dolu1990]

Deadline to propose a talk : last day of November :)

[Readon]

Rogther that, however, I am still hesitating on the topic.

[Jeff-Ciesielski]

I'll be submitting something as well, just need to narrow it down a bit :)

[Dolu1990]

doesn't has to be a slide presentation, can be a live demo

[RicardoNid]

Title: Utilizing SpinalHDL for large-scale datapath design
Abstract: Introduce the experience and case of large-scale data path design using SpinalHDL with functional programming and third-party libraries. Take a completely parallel elliptic curve adder as an example.
Estimated duration of the talk: 20 mins

[andreasWallner]

Far less interesting than most of the others - What I thought about: From Peripheral Plugins to Product documentation.
Show how we can go from a simple plugin system for bus peripherals using register file generators to documentation using custom Sphinx plugins. Also show some insight into ongoing development of a lab communication device for in-the-loop testing.

Thought about 10-15 minutes - but this might be too much Sphinx/not directly SpinalHDL related...

[sebastien-riou]

I Andreas, I think it is a very interesting topic. On my wish list the plug-in would also generate C header file as well as C test code (check reset values, access types).

[Dolu1990]

Thanks @SandmanDZ !
SpinalHDL poster

[Dolu1990]

For all the presentation, we can upload the slides in this topic.
@sebastien-riou @andreasWallner @RicardoNid @teilraum @Jeff-Ciesielski @Readon @distributed @saahm @Dolu1990

[numero-744]

@sebastien-riou Yes I'm adding Tiempo Secure, didn't ping you because I already had your confirmation.

[saahm]

Hello,

I'm updating Projects using SpinalHDL#companies (fixing the link btw). Sorry for the delay, I had to deal with my ISP because no Internet connection…

* @saahm can I add https://www.uni-bremen.de/en/ with a link to your slideshow?

* @teilraum I'm waiting for your confirmation 😉

* @distributed can I add https://hexagon.com/ with a link to your slideshow? (Btw I hope your voice is back, take care!) Notice the slideshow is marked "confidential" (bottom-left corner of slides)

* @andreasWallner I don't add anything until you tell me 😉

* @Readon can I add https://en.uestc.edu.cn/ with a link to your slideshow?

Also I think I'll rename "Companies" to "Companies & organization" to include universities. What do you think about it?

Technically no problem. Tho we are a univesity and not a company, maybe a seperate section makes sense there.
And particularly it would be our research group (http://www.informatik.uni-bremen.de/agra/ger/index.php) to be linked in that case. Slides can be linked too.

[numero-744]

@saahm Thanks I'm adding it in a new "Universities" subsection.

[teilraum]

@numero-744 Please add this link: https://www.uni-potsdam.de/en/aess/

[numero-744]

See SpinalHDL/SpinalDoc-RTD#167; tell me if I mistyped something

Preview available: https://numero-744.github.io/SpinalDoc-RTD/master/SpinalHDL/Introduction/Projects%20using%20SpinalHDL.html

I have to say; this page is much more appealing than it used to be; so I think that for companies it makes SpinalHDL much more appealing too. Thank you all!

Of course, we are still open to add other organizations. You are welcome!

@teilraum Thanks, added you to the PR

[Dolu1990]

Also, we will record the webinar to upload it somewere. Please, let's me know if it is an issue for you (you can send me private message for it, then we can cut parts out :))

[distributed]

Feel free to share my presentation in the recording.

[Dolu1990]

Here is the current time table :

Webinar timeline.xlsx

[Dolu1990]

Note, there is 10 mn between each talk. There is two reason for "such high time" :

• Allowing questions
• Allowing some presentation time overflow (to reduce stress ^^)

[Dolu1990]

Static webpage from Datenlord :
https://datenlord.github.io/en/spinal.html

[Dolu1990]

I will be connected on the call 30 mn before the start, so if you want to test that everything works you can connect too ^^

[Dolu1990]

The link to the zoom call for the webinar :
See bellow SandmanDZ message

[SandmanDZ]

Hello everyone, due to some technical issues the previous meeting number cannot be accessed, and the link to our upcoming zoom call for the webinar is as follows. Sorry for the short notice!

Webinar：Explore the SpinalHDL Landscape
Date：2022/12/16 10:00AM CET

Join Zoom meeting
https://us06web.zoom.us/j/81437673401?pwd=RUZhRWdZNW5YeC9WYWw2SWdqQnczZz09

Meeting Number：814 3767 3401
Password：1216

See you all very soon~~

[SandmanDZ]

Hello everyone, PPTs and replay videos all have been uploaded. You can access them by clicking on the pertinent button in this webpage, https://datenlord.github.io/en/spinal.html. Hope it would be of help!

[Dolu1990]

Youtube link to the replay :
https://www.youtube.com/playlist?list=PLtkg-iZSZRIx02SZsNyEq0Ih3-zM_Jy_n

[franktaTian]

Interesting！ But the link lost [https://datenlord.github.io/en/spinal.html]

[andreasWallner]

@franktaTian You can find all the recordings at the youtube link that @Dolu1990 posted above.
(https://www.youtube.com/playlist?list=PLtkg-iZSZRIx02SZsNyEq0Ih3-zM_Jy_n)

[franktaTian]

Hi，Thanks for reply. But I am not able to connect to youtobe.

[SandmanDZ]

You can find those recordings under the account of 达坦科技 on Bilibili as well.

…

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[PythonLinks]

I am considering proposing a talk on a many core Forth processor for audio.
The exact title and content to be determined based on the state of the work at the end of November. I already have 1 Mecrisp core running on the Pico-Ice, but I am just learning SpinalHDL. I am particularly mindful of the first benefit of SpinalHDL:

No more endless wiring - Create and connect complex buses like AXI in one single line.

The nature of many core applications is that each one needs different wiring, and so SpinalHDL should enable me to easily support a family of tiny Forth processors for different applications.

Here is my web site.
https://forth.pythonlinks.info/

I will keep my talk to 20 minutes plus time for questions.

[andreasWallner]

@PythonLinks while that does sound interesting, the Webinar took place December 2022, so sadly it's a bit too late

[Dolu1990]

Hi,

Note a new edition is comming :
#1235

[Dolu1990]

New edition for 2023 :
#1235

[PythonLinks]

Title: The J1Sc Family.
Speaker: Christopher Lozinski
Duration: 25 Minuts + 5 Minutes Questions.

The J1 in Scala (J1Sc) is the newest member of a large family of stack processors. When your finite state machines become too complex and you don’t have an SoC, it is time to use a soft core processor. The j1 is a small stack processor. It can run Forth, a small Reverse Polish notation programming language, Forth includes an interpreter, which is great for hardware debugging. The J1Sc Coding style will be compared with the original J1 Verilog. There are so many variants of the J1, really the only way to manage them all from a single code base is with a high level tool like SpinalHDL.

[Dolu1990]

Nice :D
Can you move your post here ?
#1235

Thanks :)

[PythonLinks]

Pico Ice Give Away
I will be giving away a Pico Ice circuit board.

The pico-ice is a small, low cost board with the Raspberry Pi Pico processor (RP2040) and a Lattice Semiconductor iCE40UP5K FPGA. The board features independent flash for the FPGA and RP2040, low power SSRAM, a couple of pushbuttons and a 3 color LED with all FPGA and RP2040 pins brought out to easy to use 0.1” header pins (arranged as Pmod’s) for fast prototyping.