Verify component without withAsync option with synchronous reset as default.

[Readon]

Closes #1430

Context, Motivation & Description

Impact on code generation

Checklist

• Unit tests were added
• API changes are or will be documented:
  • using Scaladoc comments: /** */?
  • on RTD?
  • thanks to a new tracking issue on RTD?

[Readon]

This might lead to a very slow formal verification in the lib itself.

[Readon]

The checker fails because of "multiclock on" statement would lead to an erron initial value while prove.
In theory, the initial value in prove should follow the assert and assume condition. However, when multiclock on the prove tools would not follow the initial condition.
This is tested on existing implementation and current version of yosys.

[Readon]

@Dolu1990 How can I change the default clockDomain's reset kind in Component?
Never mind, I have found the config way to achieve this.

We might need to change the default clockDomain's resetKind to SYNC for formal verification only.

[Readon]

Now the existing verification are mostly in synchronous mode, which is faster.
I would test if it works in latest yosys.

[Readon]

As tested in yosys 0.41 here, the synchronous design have been passed.
However, it failed on FifoCC tester, which turned multiclock on in a strange mode.
The waveform shows that it fails during the second reset time, the assertion does not follow the reset check priority.
It's not a proper time to upgrade to the latest version, IMO.

[Readon]

I have also moved the ModuleAnalyzer and DataAnalyzer from lib to core directory, because there might be some analysis could be easily done by those tools, also in core.

[Readon]

OK, all the verification testers have been run through under the Yosys 0.41.