Add AvalonST basic support #791
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Cool ^^ |
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Error bits are user defined so that cares the bit descriptions with the bus. Although maybe it's best not to do that for simplicity. |
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| case class AvalonSTPayload(config: AvalonSTConfig) extends Bundle { | ||
| val data: Bits = if (config.useData) Bits(config.dataWidth bit) else null |
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An shorter way is :
val data = config.useData generate Bits(config.dataWidth bits) //:)
| val valid: Bool = if (config.useValid) Bool() else null | ||
| val payload: AvalonSTPayload = AvalonSTPayload(config) | ||
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| lazy val latencyDelay: Bool = Delay(this.ready, config.readyLatency) |
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Hmm lazy val in a bundle, i'm realy not sure SpinalHDL will like it.
The goal of those signals is just to cache some values if used right ? Not realy to carry them along the bundle right ?
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Missed this. Yeah those are internal for ready tracking. Avalon as some weird timing relationships. I can un-lazy them if you think there might be problems.
Completely forgot up to now that I was working in a Bundle. XP
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Hi ^^
There is still some lazy val, can you un-lazy them ?
If you want, there is the "signalCache" API.
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Finally done. Let me know if I'm using signalCache right.
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I think this is ready. I don't personally use Avalon streams but Intel IP prefers Avalon so I think this is a nice to have as a start. |
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Good to me ^^ |
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Will do. Thanks! |
Avalon Streaming has special timing requirements and allowances which make it incompatible with Spinal streams. This PR will provide a way to model and adapt Avalon-ST between IP and Spinal streams.