Fix Igloo2 power on reset

SpinalHDL · Oct 28, 2018 · da7d79a · da7d79a
1 parent 393e05b
commit da7d79a
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Showing 4 changed files with 27 additions and 20 deletions.
diff --git a/memo.md b/memo.md
@@ -7,7 +7,7 @@ sudo apt-get install libfontconfig1:i386 libglib2.0-0:i386 libstdc++6:i386 libel
 
 sudo /sbin/modprobe dummy
 sudo /sbin/ip link set name eth0 dev dummy0
-sudo /sbin/ipconfig eth0 hw ether 08:00:27:79:ed:b1
+sudo /sbin/ifconfig eth0 hw ether 08:00:27:79:ed:b1
 
 https://electronics.stackexchange.com/questions/327527/lattice-icecube2-error-synplify-pro-321
 

diff --git a/src/main/scala/riscvSoftcoreContest/FlashXip.scala b/src/main/scala/riscvSoftcoreContest/FlashXip.scala
@@ -6,7 +6,7 @@ import spinal.lib.fsm.{State, StateMachine}
 import spinal.lib._
 import vexriscv.demo.SimpleBus
 
-case class FlashXpi(addressWidth : Int) extends Component{
+case class FlashXpi(addressWidth : Int, slowDownFactor : Int = 0) extends Component{
   val io = new Bundle {
     val bus = slave(SimpleBus(addressWidth, 32))
     val flash = master(SpiMaster())
@@ -36,15 +36,15 @@ case class FlashXpi(addressWidth : Int) extends Component{
     val SETUP, IDLE, CMD, PAYLOAD = State()
     setEntry(SETUP)
 
-    val counter = Reg(UInt(7 bits))
+    val counter = Reg(UInt(7 + slowDownFactor bits))
     counter := counter + 1
     SETUP.onEntry(counter := 0)
     SETUP.whenIsActive{
       io.flash.ss(0) := False
-      io.flash.sclk := counter.lsb
+      io.flash.sclk := counter(slowDownFactor)
       val bitstream = B"x8183"
-      io.flash.mosi := bitstream.asBools.reverse((counter >> 1).resized)
-      when(counter === widthOf(bitstream)*2-1){
+      io.flash.mosi := bitstream.asBools.reverse((counter >> 1+slowDownFactor).resized)
+      when(counter === (widthOf(bitstream)*2 << slowDownFactor)-1){
         goto(IDLE)
       }
     }
@@ -59,10 +59,10 @@ case class FlashXpi(addressWidth : Int) extends Component{
     CMD.onEntry(counter := 0)
     CMD.whenIsActive{
       io.flash.ss(0) := False
-      io.flash.sclk := counter.lsb
+      io.flash.sclk := counter(slowDownFactor)
       val bitstream = B"x0B" ## io.bus.cmd.address.resize(24 bits) ## B"x00"
-      io.flash.mosi := bitstream.asBools.reverse((counter >> 1).resized)
-      when(counter === widthOf(bitstream)*2-1){
+      io.flash.mosi := bitstream.asBools.reverse((counter >> 1+slowDownFactor).resized)
+      when(counter === (widthOf(bitstream)*2 << slowDownFactor)-1){
         io.bus.cmd.ready := True
         goto(PAYLOAD)
       }
@@ -71,9 +71,9 @@ case class FlashXpi(addressWidth : Int) extends Component{
     PAYLOAD.onEntry(counter := 0)
     PAYLOAD.whenIsActive{
       io.flash.ss(0) := False
-      io.flash.sclk := counter.lsb
-      buffer.fill setWhen(counter.lsb)
-      when(counter === 32*2-1){
+      io.flash.sclk := counter(slowDownFactor)
+      buffer.fill setWhen(counter(slowDownFactor downto 0).andR)
+      when(counter === (32*2 << slowDownFactor)-1){
         goto(IDLE)
       }
     }

diff --git a/src/main/scala/riscvSoftcoreContest/Igloo2Ip.scala b/src/main/scala/riscvSoftcoreContest/Igloo2Ip.scala
@@ -23,4 +23,8 @@ case class SYSRESET() extends BlackBox{
   val POWER_ON_RESET_N = out Bool()
 }
 
+case class SYSCTRL_RESET_STATUS() extends BlackBox{
+  val RESET_STATUS = out Bool()
+}
+
 
diff --git a/src/main/scala/riscvSoftcoreContest/Igloo2Speed.scala b/src/main/scala/riscvSoftcoreContest/Igloo2Speed.scala
@@ -168,7 +168,7 @@ case class Igloo2Speed(p : Igloo2SpeedParameters) extends Component {
 
     //Implement an counter to keep the reset mainClkResetUnbuffered high 64 cycles
     // Also this counter will automatically do a reset when the system boot.
-    val systemClkResetCounter = Reg(UInt(6 bits)) init(0)
+    val systemClkResetCounter = Reg(UInt(log2Up((p.ioClkFrequency*100.ms).toBigInt()) bits)) init(0)
     when(systemClkResetCounter =/= U(systemClkResetCounter.range -> true)){
       systemClkResetCounter := systemClkResetCounter + 1
       mainClkResetUnbuffered := True
@@ -223,7 +223,7 @@ case class Igloo2Speed(p : Igloo2SpeedParameters) extends Component {
     peripherals.io.leds <> io.leds
 
 
-    val flashXip = FlashXpi(addressWidth = 20)
+    val flashXip = FlashXpi(addressWidth = 20, slowDownFactor = 3)
     interconnect.addSlaves(
       iRam.io.bus         -> SizeMapping(0x80000000l, 64 kB),
       dRam.io.bus         -> SizeMapping(0x90000000l, 64 kB),
@@ -308,7 +308,7 @@ case class Igloo2Speed(p : Igloo2SpeedParameters) extends Component {
   }
 
   val prog = new ClockingArea(progClockDomain){
-    val ctrl = SerialRxOutput(115200,0x0F)
+    val ctrl = SerialRxOutput(115200,0x07)
     ctrl.io.serialRx := io.serialRx
     resetCtrl.systemResetBuffered setWhen(ctrl.io.output(7))
 
@@ -339,12 +339,12 @@ object Igloo2SpeedEvaluationBoard{
       val serialTx  = out  Bool()
       val serialRx  = in  Bool()
 
+//      val button = in Bool()
+
       val flashSpi  = master(SpiMaster())
-      val flashSpiProbe  = out(SpiMaster())
+      val probes  = out(Bits(8 bits))
 
       val leds = out Bits(3 bits)
-
-
     }
 
     val oscInst = osc1()
@@ -359,14 +359,17 @@ object Igloo2SpeedEvaluationBoard{
       ioClkFrequency = 25 MHz,
       ioSerialBaudRate = 115200
     ))
-
     soc.io.clk      <> cccInst.GL0
     soc.io.reset    <> !por.POWER_ON_RESET_N
     soc.io.flash    <> io.flashSpi
     soc.io.leds     <> io.leds
     soc.io.serialTx <> io.serialTx
     soc.io.serialRx <> io.serialRx
-    io.flashSpiProbe := io.flashSpi
+    io.probes(3 downto 0) := io.flashSpi.asBits
+    io.probes(4) := soc.io.reset
+    io.probes(5) := soc.io.clk
+    io.probes(6) := cccInst.LOCK
+    io.probes(7) := True
   }
 
   def main(args: Array[String]) {