GitHub - Sudeep-Dhurua/verilog-to-gate-level-synthesis: This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

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This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

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This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

verilog-hdl vlsi-cad rtl-synthesis

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