Add RegNode.is_halt_reg property

SystemRDL · Jan 20, 2022 · 7a52f3b · 7a52f3b
1 parent 28a43cf
commit 7a52f3b
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Showing 2 changed files with 20 additions and 5 deletions.
diff --git a/systemrdl/core/properties.py b/systemrdl/core/properties.py
@@ -1642,15 +1642,15 @@ def validate(self, node: m_node.Node, value: Any) -> None:
                 self.env.msg.error(
                     "Use of a hardware write-enable on field '%s' does not make "
                     "sense because it is defined as 'sticky'. Sticky fields already "
-                    "define their own hardware write-enable behavior."
+                    "implicitly control their hardware write-enable behavior based on the input value."
                     % (node.inst_name),
                     node.inst.property_src_ref.get('we', node.inst.inst_src_ref)
                 )
             if node.get_property('wel'):
                 self.env.msg.error(
                     "Use of a hardware write-enable on field '%s' does not make "
                     "sense because it is defined as 'sticky'. Sticky fields already "
-                    "define their own hardware write-enable behavior."
+                    "implicitly control their hardware write-enable behavior based on the input value."
                     % (node.inst_name),
                     node.inst.property_src_ref.get('wel', node.inst.inst_src_ref)
                 )
@@ -1686,15 +1686,15 @@ def validate(self, node: m_node.Node, value: Any) -> None:
                 self.env.msg.error(
                     "Use of a hardware write-enable on field '%s' does not make "
                     "sense because it is defined as 'stickybit'. Stickybit fields already "
-                    "define their own hardware write-enable behavior."
+                    "implicitly control their hardware write-enable behavior based on the input value."
                     % (node.inst_name),
                     node.inst.property_src_ref.get('we', node.inst.inst_src_ref)
                 )
             if node.get_property('wel'):
                 self.env.msg.error(
                     "Use of a hardware write-enable on field '%s' does not make "
                     "sense because it is defined as 'stickybit'. Stickybit fields already "
-                    "define their own hardware write-enable behavior."
+                    "implicitly control their hardware write-enable behavior based on the input value."
                     % (node.inst_name),
                     node.inst.property_src_ref.get('wel', node.inst.inst_src_ref)
                 )

diff --git a/systemrdl/node.py b/systemrdl/node.py
@@ -1220,7 +1220,8 @@ def has_hw_readable(self) -> bool:
     @property
     def is_interrupt_reg(self) -> bool:
         """
-        Register contains one or more interrupt fields.
+        Register contains one or more interrupt fields and therefore produces an
+        interrupt output signal.
 
 
         .. versionadded:: 1.22
@@ -1230,6 +1231,20 @@ def is_interrupt_reg(self) -> bool:
                 return True
         return False
 
+    @property
+    def is_halt_reg(self) -> bool:
+        """
+        Register contains one or more interrupt fields that use ``haltenable``
+        or ``haltmask`` and therefore produces a halt output signal.
+
+
+        .. versionadded:: 1.22
+        """
+        for field in self.fields():
+            if field.get_property('haltenable') or field.get_property('haltmask'):
+                return True
+        return False
+
 #===============================================================================
 class RegfileNode(AddressableNode):