Merge pull request #2043 from The-OpenROAD-Project-staging/rm-no-attr

Remove -noattr from write_verilog in yosys
The-OpenROAD-Project · Jun 6, 2024 · c1a0f94 · c1a0f94
2 parents f93858a + 84ee6da
commit c1a0f94
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl
@@ -92,4 +92,4 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
 tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
 
 # Write synthesized design
-write_verilog -noattr -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v
+write_verilog -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v