SDC constraints on internal pins

[gkamendje]

I am using Openroad in the ORFS flow and I was wondering how to access internal pins while setting SDC constrains. I would like for example to set a false path to the Test Enable pin of clock gating cells using a syntax similar to this: set_false_path -to [get_pins u1_inst/u2_inst/u3_inst/TE] I have tried variants such as set_false_path -to [get_pins u1_inst?u2_inst?u3_inst?TE] or even set_false_path -to [get_pins u1_inst*u2_inst*u3_inst*TE] . I get the error [WARNING STA-0335] pin 'u1_inst/u2_inst/u3_inst/TE' not found. at various steps of the flow.
On a similar note I was wondering if there would be a recommended way to create generated clocks on internal nodes. I have looked at many of the example designs but none of them seems to define generated clock in the contraints files. All the contrains I have seen so far apply to ports only.

[maliberty]

In OR we flatten the netlist so you can only use leaf pins. This is an area we intend to improve in the future.

[gkamendje]

How would you then set contraints to create a generated clock on an internal clock divider or a PLL macro?

[maliberty]

On a leaf pin the drives the hierarchical pin you would otherwise use.

[gkamendje]

Hmm... in my case I see that the endpoints driven by the internal clocks (with the clock defined on the leaf pins) are reported as unconstrained. Is there anything I should do besides creating the clock in the SDC file?

[maliberty]

There is nothing particular. It would be easier to investigate with a test case. If you can provide one then please open an issue.

[gkamendje]

OK I just open #1587

[gkamendje]

Closing since it is solved in #1587