OpenROAD config.mk for combinational logic synthesis

[ishwars1618]

Hello, I am a beginner trying to use OpenROAD flow scripts for simple designs and starting with synthesizing a combinational logic circuit without any clock. I am trying to adapt the scripts for the gcd example. However, my design does not have a clock. How do I specify that there is no clk signal (though I could have a clock period) in the constraint.sdc file?

[maliberty]

You just leave off the optional pin list: create_clock -name <name>-period <period>

[ishwars1618]

Thanks! Can I still set clock period (for reasons of computing slack etc.)?

[maliberty]

Yes, the formatting was a bit messed up in my comment so I fixed it. You'll have to have timings on your i/o pins relative to clock in order to get slacks.

[ishwars1618]

So I should not give the create_clock directive, correct? Because if I give create_clock with just the -period option without the -name and its value, I get an error. Also, if all my input pins are arriving at time 0, how do I specify that relative to a clock (since I don't have a clock input)?

[maliberty]

You should give it a name but that name is arbitrary. You should just leave off any pins to connect it to. Then your inputs can reference that name.

[vijayank88]

@maliberty Is below format ok for combinational circuits?

set clk_name  virtual_clk
set clk_port_name ""
set clk_period 8.0 
set clk_io_pct 0.2

set clk_port [get_ports $clk_port_name]

create_clock -name $clk_name -period $clk_period $clk_port

[maliberty]

There is no need for clk_port or clk_port_name

[vijayank88]

create_clock -name virtual_clock -period 10