1-bit full adder combinational circuit

[visionvlsi]

Please help me,
why is that I am unable to run the flow on 1-bit full adder. I am following correct directory structure and my config file contents are:

export DESIGN_NICKNAME = fa
export DESIGN_NAME = fa
export PLATFORM = sky130hd
export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/fa.v
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export DIE_AREA = 0 0 100 100
export CORE_AREA = 5 5 90 90

Since constraints file is must I just kept in constraint.sdc

---

current_design fa
create_clock -period 100 -name virtual_clock

[rovinski]

It's impossible to know without knowing the error. Please post your log.

[vijayank88]

@rovinski This is the error

[maliberty]

The error is tell you that the block is to small to fit any met4 grid. You should increase the area of the block (or reduce the power grid).

[visionvlsi]

That is correct. How do I do either of the two reasons stated? Please let me know, I wanna try that.

[maliberty]

See https://openroad-flow-scripts.readthedocs.io/en/latest/user/FlowVariables.html
in particular the floorplan variables. You can either set the area with DIE_AREA/CORE_AREA or CORE_UTILIZATION/CORE_MARGIN