Mock array element simpler constraints sdc

[oharboe]

This is an attempt to simplify mock-array/Element/constraints.sdc

From the following observations, all else follows: the only thing that can fail timing closure, is a register to register path. All other constraints gives the flow an optimization target. Failure to meet the timing constraint of an optimization target constraint is not a timing closure failure.

Note that ORFS regression checks does not have the ability to distinguish between timing closure failures(register to register paths) and optimization constraints violations(which may or may not cause timing violations later on higher up in mock-array).

For the Element constraint.sdc, the only register to register path are within the Element(recently added) and no lowe level macros are involved. These have to be checked at the Element level as they are invisible higher up in mock-array.

As for the remaining optimization constraints for Element, they should be for through paths and from input pins to register and from register to output pins.

The clock latency & tree should be ignored as far constraints go; it is not part of the optimization constraints and is accounted for in register to register paths timing closure paths within the Element. Also the clock tree higher up will take the clock tree insertion latency of the Element into account when balancing the clock tree.

The timing closure for the register to register paths between Elements is checked at the mock-array level. 

With this in mind, the constraints.sdc file for the Element becomes quite general and simple. set_max_delay is used exclusively for optimization constraints and the clock period is used to check timing closure for register to register paths. set_input/output_delay are not used.

[oharboe]

mock-array/Element has no timing closure failures when looking at register to register paths.

There are timing violations for the optimization targets, but no hold cells are added:

>>> report_checks -from [all_registers] -to [all_registers] -path_delay min
Startpoint: REG[4]$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left[4]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  78.58   78.58   clock network delay (propagated)
   0.00   78.58 ^ REG[4]$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  44.51  123.09 ^ REG[4]$_DFF_P_/QN (DFFHQNx2_ASAP7_75t_R)
   9.46  132.55 v _0903_/Y (NAND2x1_ASAP7_75t_R)
   0.09  132.64 v io_outs_left[4]$_DFF_P_/D (DFFHQNx3_ASAP7_75t_R)
         132.64   data arrival time

   0.00    0.00   clock clock (rise edge)
  88.23   88.23   clock network delay (propagated)
  20.00  108.23   clock uncertainty
  -3.01  105.22   clock reconvergence pessimism
         105.22 ^ io_outs_left[4]$_DFF_P_/CLK (DFFHQNx3_ASAP7_75t_R)
  14.33  119.54   library hold time
         119.54   data required time
---------------------------------------------------------
         119.54   data required time
        -132.64   data arrival time
---------------------------------------------------------
          13.10   slack (MET)


>>> report_checks -from [all_registers] -to [all_registers] -path_delay max
Startpoint: REG_1[20]$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left[20]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  85.25   85.25   clock network delay (propagated)
   0.00   85.25 ^ REG_1[20]$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  52.74  137.99 v REG_1[20]$_DFF_P_/QN (DFFHQNx2_ASAP7_75t_R)
  24.93  162.92 ^ _0919_/Y (NAND2x1_ASAP7_75t_R)
   0.97  163.89 ^ io_outs_left[20]$_DFF_P_/D (DFFHQNx3_ASAP7_75t_R)
         163.89   data arrival time

 250.00  250.00   clock clock (rise edge)
  78.91  328.91   clock network delay (propagated)
 -20.00  308.91   clock uncertainty
   0.62  309.53   clock reconvergence pessimism
         309.53 ^ io_outs_left[20]$_DFF_P_/CLK (DFFHQNx3_ASAP7_75t_R)
 -12.49  297.05   library setup time
         297.05   data required time
---------------------------------------------------------
         297.05   data required time
        -163.89   data arrival time
---------------------------------------------------------
         133.16   slack (MET)

[oharboe]

Looks good for mock-array:

make DESIGN_CONFIG=designs/asap7/mock-array/config.mk
make DESIGN_CONFIG=designs/asap7/mock-array/config.mk gui_final

>>> report_checks -from [all_registers] -to [all_registers] -path_delay min
Startpoint: ces_5_7 (rising edge-triggered flip-flop clocked by clock)
Endpoint: ces_6_7 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 229.57  229.57   clock network delay (propagated)
   0.00  229.57 ^ ces_5_7/clock (Element)
 144.05  373.62 v ces_5_7/io_outs_up[62] (Element)
   0.21  373.83 v ces_6_7/io_ins_up[62] (Element)
         373.83   data arrival time

   0.00    0.00   clock clock (rise edge)
 254.51  254.51   clock network delay (propagated)
  20.00  274.51   clock uncertainty
  -7.25  267.26   clock reconvergence pessimism
         267.26 ^ ces_6_7/clock (Element)
  84.16  351.42   library hold time
         351.42   data required time
---------------------------------------------------------
         351.42   data required time
        -373.83   data arrival time
---------------------------------------------------------
          22.41   slack (MET)


>>> report_checks -from [all_registers] -to [all_registers] -path_delay max
Startpoint: ces_7_1 (rising edge-triggered flip-flop clocked by clock)
Endpoint: ces_7_5 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 249.83  249.83   clock network delay (propagated)
   0.00  249.83 ^ ces_7_1/clock (Element)
 161.12  410.96 ^ ces_7_1/io_lsbOuts_7 (Element)
  37.79  448.75 ^ ces_7_2/io_lsbOuts_6 (Element)
  40.77  489.52 ^ ces_7_3/io_lsbOuts_5 (Element)
  32.74  522.26 ^ ces_7_4/io_lsbOuts_4 (Element)
   0.00  522.26 ^ ces_7_5/io_lsbIns_4 (Element)
         522.26   data arrival time

 250.00  250.00   clock clock (rise edge)
 231.74  481.74   clock network delay (propagated)
 -20.00  461.74   clock uncertainty
   6.17  467.91   clock reconvergence pessimism
         467.91 ^ ces_7_5/clock (Element)
  48.28  516.20   library setup time
         516.20   data required time
---------------------------------------------------------
         516.20   data required time
        -522.26   data arrival time
---------------------------------------------------------
          -6.06   slack (VIOLATED)

[oharboe]

Looks good for mock-array/Element:

make DESIGN_CONFIG=designs/asap7/mock-array/config.mk
make DESIGN_CONFIG=designs/asap7/mock-array/config.mk gui_final

>>> report_checks -from [all_registers] -to [all_registers] -path_delay min
Startpoint: REG_4[57]$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_right[57]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  76.73   76.73   clock network delay (propagated)
   0.00   76.73 ^ REG_4[57]$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  45.80  122.53 ^ REG_4[57]$_DFF_P_/QN (DFFHQNx2_ASAP7_75t_R)
  10.45  132.98 v _0828_/Y (NAND2x1_ASAP7_75t_R)
   0.03  133.01 v io_outs_right[57]$_DFF_P_/D (DFFHQNx3_ASAP7_75t_R)
         133.01   data arrival time

   0.00    0.00   clock clock (rise edge)
  85.62   85.62   clock network delay (propagated)
  20.00  105.62   clock uncertainty
  -0.60  105.03   clock reconvergence pessimism
         105.03 ^ io_outs_right[57]$_DFF_P_/CLK (DFFHQNx3_ASAP7_75t_R)
  12.51  117.53   library hold time
         117.53   data required time
---------------------------------------------------------
         117.53   data required time
        -133.01   data arrival time
---------------------------------------------------------
          15.48   slack (MET)


>>> report_checks -from [all_registers] -to [all_registers] -path_delay max
Startpoint: REG_1[18]$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_outs_left[18]$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
  90.70   90.70   clock network delay (propagated)
   0.00   90.70 ^ REG_1[18]$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  58.60  149.30 v REG_1[18]$_DFF_P_/QN (DFFHQNx2_ASAP7_75t_R)
  28.34  177.64 ^ _0917_/Y (NAND2x1_ASAP7_75t_R)
   0.67  178.31 ^ io_outs_left[18]$_DFF_P_/D (DFFHQNx1_ASAP7_75t_R)
         178.31   data arrival time

 250.00  250.00   clock clock (rise edge)
  79.90  329.90   clock network delay (propagated)
 -20.00  309.90   clock uncertainty
   2.91  312.80   clock reconvergence pessimism
         312.80 ^ io_outs_left[18]$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
 -11.92  300.88   library setup time
         300.88   data required time
---------------------------------------------------------
         300.88   data required time
        -178.31   data arrival time
---------------------------------------------------------
         122.58   slack (MET)

[oharboe]

@rovinski What do you think about this approach for architectural exploration?

Architectural exploration, the goal of mock-array, is a completely separate concern to an actual tape-out.

For an actual tape-out I would expect sharper(more accurate and precise) more macro and context specific constraints.sdc files would be used.

[tspyrou]

SDC is a rich language and I think its great that you are able to have a simple SDC like this to cover both cases and constrain the design to work the way you want it.

[rovinski]

max_delay should probably be a percentage of the clock, because if the clock scales down, the IO timing needs to scale as well. Otherwise it seems good for architectural exploration.

[oharboe]

max_delay should probably be a percentage of the clock, because if the clock scales down, the IO timing needs to scale as well. Otherwise it seems good for architectural exploration.

Sounds good. I want to leave that as a future improvement as I'm a little bit unsure that it is true. What I'm trying to do is to ask the optimizer to do it's best for a macro where the inputs/outputs are registered. I'm wondering if these numbers are in fact constants that relate to how long it takes for the PDK to go through the input/output buffers.

I'm loath to add comments about this to the constraints.sdc, because it is a bit early days in my understanding. ChatGPT would probably write something more comprehensible than the drivel that I could currently come up with with my current understanding... :-)