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new designs
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@mattvenn
mattvenn committed Apr 18, 2023
1 parent 2796ef4 commit f70b2df
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Showing 67 changed files with 667,245 additions and 312,827 deletions.
1 change: 1 addition & 0 deletions .gitignore
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Expand Up @@ -20,3 +20,4 @@ verilog/gl/all_sta.tcl
verilog/gl/merged_user_project_wrapper.v
verilog/gl/sta.sh
verilog/gl/user_project_wrapper.v_edited
spef/user_project_wrapper.tcl
6 changes: 6 additions & 0 deletions README.md
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Expand Up @@ -60,3 +60,9 @@ For the most recent automatic build, click the tt_datasheet badge above, then do
| 34 | Grant Hernandez (@grant-h) | CRC Decelerator | HDL | https://github.com/grant-h/tt03-crc-decelerator |
| 35 | Matt Venn | 7 segment seconds | HDL | https://github.com/nikor/tt03-verilog-demo |
| 36 | Norberto Hernandez-Como | Binary to DEC and HEX | [Wokwi](https://wokwi.com/projects/361684719151591425) | https://github.com/jedicomo22/Norberto_IPN_V1 |
| 37 | Uri Shaked | Simon Says | HDL | https://github.com/wokwi/tt03-simon-game |
| 38 | Dakotath | Shift Register Ram | [Wokwi](https://wokwi.com/projects/360295047631610881) | https://github.com/dakotath/tt03-submission-template |
| 39 | Emmanouel Matigakis | tinysat | HDL | https://github.com/emmatigakis/tt03-tinysat |
| 41 | Balint Kovacs | POV display | HDL | https://github.com/dratini0/tt03-pov-display |
| 42 | jordan336 | Toy CPU | HDL | https://github.com/jordan336/tt03-toy-cpu |
| 43 | Daniel Wisehart | Base-10 grey counter from 0-9999 | HDL | https://github.com/dwisehart/tt03-submission |
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13,826 changes: 6,872 additions & 6,954 deletions def/user_project_wrapper.def
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88 changes: 44 additions & 44 deletions lef/MichaelBell_6bit_fifo.lef
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Expand Up @@ -179,52 +179,52 @@ MACRO MichaelBell_6bit_fifo
LAYER li1 ;
RECT 5.520 5.355 144.440 163.285 ;
LAYER met1 ;
RECT 0.530 4.460 146.210 167.920 ;
RECT 1.450 3.780 145.750 166.900 ;
LAYER met2 ;
RECT 0.550 4.430 146.180 167.950 ;
LAYER met3 ;
RECT 0.270 162.200 145.230 163.365 ;
RECT 2.400 160.800 145.230 162.200 ;
RECT 0.270 152.000 145.230 160.800 ;
RECT 2.400 150.600 145.230 152.000 ;
RECT 0.270 141.800 145.230 150.600 ;
RECT 2.400 140.400 145.230 141.800 ;
RECT 0.270 131.600 145.230 140.400 ;
RECT 2.400 130.200 145.230 131.600 ;
RECT 0.270 121.400 145.230 130.200 ;
RECT 2.400 120.000 145.230 121.400 ;
RECT 0.270 111.200 145.230 120.000 ;
RECT 2.400 109.800 145.230 111.200 ;
RECT 0.270 101.000 145.230 109.800 ;
RECT 2.400 99.600 145.230 101.000 ;
RECT 0.270 90.800 145.230 99.600 ;
RECT 2.400 89.400 145.230 90.800 ;
RECT 0.270 80.600 145.230 89.400 ;
RECT 2.400 79.200 145.230 80.600 ;
RECT 0.270 70.400 145.230 79.200 ;
RECT 2.400 69.000 145.230 70.400 ;
RECT 0.270 60.200 145.230 69.000 ;
RECT 2.400 58.800 145.230 60.200 ;
RECT 0.270 50.000 145.230 58.800 ;
RECT 2.400 48.600 145.230 50.000 ;
RECT 0.270 39.800 145.230 48.600 ;
RECT 2.400 38.400 145.230 39.800 ;
RECT 0.270 29.600 145.230 38.400 ;
RECT 2.400 28.200 145.230 29.600 ;
RECT 0.270 19.400 145.230 28.200 ;
RECT 2.400 18.000 145.230 19.400 ;
RECT 0.270 9.200 145.230 18.000 ;
RECT 2.400 7.800 145.230 9.200 ;
RECT 0.270 5.275 145.230 7.800 ;
RECT 1.470 3.750 145.730 166.930 ;
LAYER met3 ;
RECT 0.270 162.200 145.755 163.365 ;
RECT 2.400 160.800 145.755 162.200 ;
RECT 0.270 152.000 145.755 160.800 ;
RECT 2.400 150.600 145.755 152.000 ;
RECT 0.270 141.800 145.755 150.600 ;
RECT 2.400 140.400 145.755 141.800 ;
RECT 0.270 131.600 145.755 140.400 ;
RECT 2.400 130.200 145.755 131.600 ;
RECT 0.270 121.400 145.755 130.200 ;
RECT 2.400 120.000 145.755 121.400 ;
RECT 0.270 111.200 145.755 120.000 ;
RECT 2.400 109.800 145.755 111.200 ;
RECT 0.270 101.000 145.755 109.800 ;
RECT 2.400 99.600 145.755 101.000 ;
RECT 0.270 90.800 145.755 99.600 ;
RECT 2.400 89.400 145.755 90.800 ;
RECT 0.270 80.600 145.755 89.400 ;
RECT 2.400 79.200 145.755 80.600 ;
RECT 0.270 70.400 145.755 79.200 ;
RECT 2.400 69.000 145.755 70.400 ;
RECT 0.270 60.200 145.755 69.000 ;
RECT 2.400 58.800 145.755 60.200 ;
RECT 0.270 50.000 145.755 58.800 ;
RECT 2.400 48.600 145.755 50.000 ;
RECT 0.270 39.800 145.755 48.600 ;
RECT 2.400 38.400 145.755 39.800 ;
RECT 0.270 29.600 145.755 38.400 ;
RECT 2.400 28.200 145.755 29.600 ;
RECT 0.270 19.400 145.755 28.200 ;
RECT 2.400 18.000 145.755 19.400 ;
RECT 0.270 9.200 145.755 18.000 ;
RECT 2.400 7.800 145.755 9.200 ;
RECT 0.270 5.275 145.755 7.800 ;
LAYER met4 ;
RECT 0.295 8.335 21.685 162.345 ;
RECT 24.085 8.335 39.050 162.345 ;
RECT 41.450 8.335 56.415 162.345 ;
RECT 58.815 8.335 73.780 162.345 ;
RECT 76.180 8.335 91.145 162.345 ;
RECT 93.545 8.335 108.510 162.345 ;
RECT 110.910 8.335 125.875 162.345 ;
RECT 128.275 8.335 136.785 162.345 ;
RECT 0.295 6.295 21.685 160.305 ;
RECT 24.085 6.295 39.050 160.305 ;
RECT 41.450 6.295 56.415 160.305 ;
RECT 58.815 6.295 73.780 160.305 ;
RECT 76.180 6.295 91.145 160.305 ;
RECT 93.545 6.295 108.510 160.305 ;
RECT 110.910 6.295 125.875 160.305 ;
RECT 128.275 6.295 134.945 160.305 ;
END
END MichaelBell_6bit_fifo
END LIBRARY
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230 changes: 230 additions & 0 deletions lef/dratini0_pov_display_top.lef
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@@ -0,0 +1,230 @@
VERSION 5.7 ;
NOWIREEXTENSIONATPIN ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
MACRO dratini0_pov_display_top
CLASS BLOCK ;
FOREIGN dratini0_pov_display_top ;
ORIGIN 0.000 0.000 ;
SIZE 150.000 BY 170.000 ;
PIN io_in[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 8.200 2.000 8.800 ;
END
END io_in[0]
PIN io_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 18.400 2.000 19.000 ;
END
END io_in[1]
PIN io_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 28.600 2.000 29.200 ;
END
END io_in[2]
PIN io_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 38.800 2.000 39.400 ;
END
END io_in[3]
PIN io_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 49.000 2.000 49.600 ;
END
END io_in[4]
PIN io_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 59.200 2.000 59.800 ;
END
END io_in[5]
PIN io_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 69.400 2.000 70.000 ;
END
END io_in[6]
PIN io_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 79.600 2.000 80.200 ;
END
END io_in[7]
PIN io_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 89.800 2.000 90.400 ;
END
END io_out[0]
PIN io_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 100.000 2.000 100.600 ;
END
END io_out[1]
PIN io_out[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 110.200 2.000 110.800 ;
END
END io_out[2]
PIN io_out[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 120.400 2.000 121.000 ;
END
END io_out[3]
PIN io_out[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 130.600 2.000 131.200 ;
END
END io_out[4]
PIN io_out[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 140.800 2.000 141.400 ;
END
END io_out[5]
PIN io_out[6]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 151.000 2.000 151.600 ;
END
END io_out[6]
PIN io_out[7]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
PORT
LAYER met3 ;
RECT 0.000 161.200 2.000 161.800 ;
END
END io_out[7]
PIN vccd1
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met4 ;
RECT 22.085 5.200 23.685 163.440 ;
END
PORT
LAYER met4 ;
RECT 56.815 5.200 58.415 163.440 ;
END
PORT
LAYER met4 ;
RECT 91.545 5.200 93.145 163.440 ;
END
PORT
LAYER met4 ;
RECT 126.275 5.200 127.875 163.440 ;
END
END vccd1
PIN vssd1
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met4 ;
RECT 39.450 5.200 41.050 163.440 ;
END
PORT
LAYER met4 ;
RECT 74.180 5.200 75.780 163.440 ;
END
PORT
LAYER met4 ;
RECT 108.910 5.200 110.510 163.440 ;
END
PORT
LAYER met4 ;
RECT 143.640 5.200 145.240 163.440 ;
END
END vssd1
OBS
LAYER li1 ;
RECT 5.520 5.355 144.440 163.285 ;
LAYER met1 ;
RECT 2.370 3.780 145.750 164.860 ;
LAYER met2 ;
RECT 2.390 3.750 145.720 164.890 ;
LAYER met3 ;
RECT 2.000 162.200 145.230 163.365 ;
RECT 2.400 160.800 145.230 162.200 ;
RECT 2.000 152.000 145.230 160.800 ;
RECT 2.400 150.600 145.230 152.000 ;
RECT 2.000 141.800 145.230 150.600 ;
RECT 2.400 140.400 145.230 141.800 ;
RECT 2.000 131.600 145.230 140.400 ;
RECT 2.400 130.200 145.230 131.600 ;
RECT 2.000 121.400 145.230 130.200 ;
RECT 2.400 120.000 145.230 121.400 ;
RECT 2.000 111.200 145.230 120.000 ;
RECT 2.400 109.800 145.230 111.200 ;
RECT 2.000 101.000 145.230 109.800 ;
RECT 2.400 99.600 145.230 101.000 ;
RECT 2.000 90.800 145.230 99.600 ;
RECT 2.400 89.400 145.230 90.800 ;
RECT 2.000 80.600 145.230 89.400 ;
RECT 2.400 79.200 145.230 80.600 ;
RECT 2.000 70.400 145.230 79.200 ;
RECT 2.400 69.000 145.230 70.400 ;
RECT 2.000 60.200 145.230 69.000 ;
RECT 2.400 58.800 145.230 60.200 ;
RECT 2.000 50.000 145.230 58.800 ;
RECT 2.400 48.600 145.230 50.000 ;
RECT 2.000 39.800 145.230 48.600 ;
RECT 2.400 38.400 145.230 39.800 ;
RECT 2.000 29.600 145.230 38.400 ;
RECT 2.400 28.200 145.230 29.600 ;
RECT 2.000 19.400 145.230 28.200 ;
RECT 2.400 18.000 145.230 19.400 ;
RECT 2.000 9.200 145.230 18.000 ;
RECT 2.400 7.800 145.230 9.200 ;
RECT 2.000 5.275 145.230 7.800 ;
LAYER met4 ;
RECT 26.975 128.695 39.050 161.665 ;
RECT 41.450 128.695 56.415 161.665 ;
RECT 58.815 128.695 73.780 161.665 ;
RECT 76.180 128.695 91.145 161.665 ;
RECT 93.545 128.695 108.510 161.665 ;
RECT 110.910 128.695 125.875 161.665 ;
RECT 128.275 128.695 134.945 161.665 ;
END
END dratini0_pov_display_top
END LIBRARY

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