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feat: update project tt_um_nickjhay_processor from nickjhay/tt05-subm…
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…ission-template

Commit: f4e0d2db7a1876bb6e601dba1b7b3c7966c6432f
Workflow: https://github.com/nickjhay/tt05-submission-template/actions/runs/6756272108
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 4, 2023
1 parent 1af4066 commit 3543b15
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Showing 7 changed files with 54,646 additions and 48,682 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_nickjhay_processor/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt05 98e7cb27",
"repo": "https://github.com/nickjhay/tt05-submission-template",
"commit": "b29c29d459b1a3b305b3899994e7943f387f1d51",
"workflow_url": "https://github.com/nickjhay/tt05-submission-template/actions/runs/6751368229",
"commit": "f4e0d2db7a1876bb6e601dba1b7b3c7966c6432f",
"workflow_url": "https://github.com/nickjhay/tt05-submission-template/actions/runs/6756272108",
"sort_id": 1698707780092,
"openlane_version": "OpenLane 7e5a2e9fb274c0a100b4859a927adce7089455ff",
"power_gate": false
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2 changes: 1 addition & 1 deletion projects/tt_um_nickjhay_processor/metrics.csv
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_nickjhay_processor,wokwi,flow completed,0h3m9s0ms,0h2m39s0ms,131341.32536243816,0.0187755072,65670.66268121908,61.83,-1,587.89,936,0,0,0,0,0,0,0,0,0,0,-1,-1,27700,8648,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,15447284.0,0.0,53.15,43.28,9.71,0.72,-1,1035,1225,598,776,0,0,0,664,73,5,4,1,133,65,2,148,217,212,7,523,246,4,369,1233,2375,17274.0672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,40.710,0.3,1,10,0.7,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_nickjhay_processor,wokwi,flow completed,0h9m9s0ms,0h8m18s0ms,136880.45668348178,0.0187755072,68440.22834174089,66.14,-1,622.51,1071,0,0,0,0,0,0,0,0,0,0,-1,-1,31827,9516,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,17338717.0,0.0,53.82,44.03,15.96,4.49,-1,1349,1530,668,849,0,0,0,900,89,0,10,6,181,69,1,282,217,209,9,453,246,7,417,1285,2408,17274.0672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,40.710,0.3,1,10,0.8,0,sky130_fd_sc_hd,AREA 0
81 changes: 50 additions & 31 deletions projects/tt_um_nickjhay_processor/synthesis-stats.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -3,42 +3,61 @@

=== tt_um_nickjhay_processor ===

Number of wires: 920
Number of wire bits: 955
Number of public wires: 212
Number of public wire bits: 247
Number of wires: 1055
Number of wire bits: 1090
Number of public wires: 209
Number of public wire bits: 244
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 936
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21o_2 2
sky130_fd_sc_hd__a21oi_2 1
sky130_fd_sc_hd__a22o_2 71
sky130_fd_sc_hd__a31o_2 66
Number of cells: 1071
sky130_fd_sc_hd__a2111o_2 6
sky130_fd_sc_hd__a211o_2 5
sky130_fd_sc_hd__a211oi_2 2
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21o_2 17
sky130_fd_sc_hd__a21oi_2 68
sky130_fd_sc_hd__a221o_2 11
sky130_fd_sc_hd__a22o_2 122
sky130_fd_sc_hd__a2bb2o_2 2
sky130_fd_sc_hd__a311o_2 5
sky130_fd_sc_hd__a31o_2 22
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__and2_2 59
sky130_fd_sc_hd__and3_2 12
sky130_fd_sc_hd__and3b_2 66
sky130_fd_sc_hd__and4_2 1
sky130_fd_sc_hd__and4b_2 1
sky130_fd_sc_hd__and4bb_2 2
sky130_fd_sc_hd__buf_1 101
sky130_fd_sc_hd__a41o_2 1
sky130_fd_sc_hd__and2_2 62
sky130_fd_sc_hd__and2b_2 3
sky130_fd_sc_hd__and3_2 70
sky130_fd_sc_hd__and3b_2 2
sky130_fd_sc_hd__buf_1 142
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfxtp_2 204
sky130_fd_sc_hd__inv_2 70
sky130_fd_sc_hd__mux2_2 2
sky130_fd_sc_hd__nand2_2 1
sky130_fd_sc_hd__nand4_2 65
sky130_fd_sc_hd__nor2_2 3
sky130_fd_sc_hd__o2111a_2 1
sky130_fd_sc_hd__o211a_2 64
sky130_fd_sc_hd__o21a_2 65
sky130_fd_sc_hd__o31a_2 56
sky130_fd_sc_hd__dfxtp_2 201
sky130_fd_sc_hd__inv_2 11
sky130_fd_sc_hd__mux2_2 44
sky130_fd_sc_hd__mux4_2 1
sky130_fd_sc_hd__nand2_2 57
sky130_fd_sc_hd__nand2b_2 2
sky130_fd_sc_hd__nand3_2 20
sky130_fd_sc_hd__nand4_2 5
sky130_fd_sc_hd__nor2_2 81
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__nor3b_2 1
sky130_fd_sc_hd__o211a_2 34
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_2 7
sky130_fd_sc_hd__o21ai_2 9
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 3
sky130_fd_sc_hd__o221ai_2 1
sky130_fd_sc_hd__o311a_2 4
sky130_fd_sc_hd__o31a_2 2
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__or2_2 2
sky130_fd_sc_hd__or3_2 1
sky130_fd_sc_hd__or4bb_2 1
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 8
sky130_fd_sc_hd__or2b_2 1
sky130_fd_sc_hd__or3_2 4
sky130_fd_sc_hd__or3b_2 5
sky130_fd_sc_hd__or4_2 1
sky130_fd_sc_hd__xnor2_2 1

Chip area for module '\tt_um_nickjhay_processor': 10308.636800
Chip area for module '\tt_um_nickjhay_processor': 11028.076800

Binary file modified projects/tt_um_nickjhay_processor/tt_um_nickjhay_processor.gds
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134 changes: 70 additions & 64 deletions projects/tt_um_nickjhay_processor/tt_um_nickjhay_processor.lef
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 137.390 110.520 137.690 111.520 ;
Expand All @@ -95,7 +95,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[2]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 134.630 110.520 134.930 111.520 ;
Expand All @@ -104,7 +104,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 131.870 110.520 132.170 111.520 ;
Expand All @@ -122,7 +122,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 126.350 110.520 126.650 111.520 ;
Expand All @@ -131,7 +131,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[6]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 123.590 110.520 123.890 111.520 ;
Expand All @@ -140,7 +140,7 @@ MACRO tt_um_nickjhay_processor
PIN ui_in[7]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.196500 ;
PORT
LAYER met4 ;
RECT 120.830 110.520 121.130 111.520 ;
Expand All @@ -158,7 +158,7 @@ MACRO tt_um_nickjhay_processor
PIN uio_in[1]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
ANTENNAGATEAREA 0.159000 ;
PORT
LAYER met4 ;
RECT 115.310 110.520 115.610 111.520 ;
Expand All @@ -176,6 +176,7 @@ MACRO tt_um_nickjhay_processor
PIN uio_in[3]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.126000 ;
PORT
LAYER met4 ;
RECT 109.790 110.520 110.090 111.520 ;
Expand All @@ -184,6 +185,7 @@ MACRO tt_um_nickjhay_processor
PIN uio_in[4]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
PORT
LAYER met4 ;
RECT 107.030 110.520 107.330 111.520 ;
Expand All @@ -192,6 +194,7 @@ MACRO tt_um_nickjhay_processor
PIN uio_in[5]
DIRECTION INPUT ;
USE SIGNAL ;
ANTENNAGATEAREA 0.213000 ;
PORT
LAYER met4 ;
RECT 104.270 110.520 104.570 111.520 ;
Expand Down Expand Up @@ -344,7 +347,7 @@ MACRO tt_um_nickjhay_processor
PIN uo_out[0]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 95.990 110.520 96.290 111.520 ;
Expand All @@ -353,7 +356,7 @@ MACRO tt_um_nickjhay_processor
PIN uo_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.462000 ;
PORT
LAYER met4 ;
RECT 93.230 110.520 93.530 111.520 ;
Expand Down Expand Up @@ -389,7 +392,7 @@ MACRO tt_um_nickjhay_processor
PIN uo_out[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 1.242000 ;
PORT
LAYER met4 ;
RECT 82.190 110.520 82.490 111.520 ;
Expand Down Expand Up @@ -417,62 +420,65 @@ MACRO tt_um_nickjhay_processor
LAYER li1 ;
RECT 2.760 2.635 165.600 108.885 ;
LAYER met1 ;
RECT 2.460 2.480 166.400 111.480 ;
RECT 2.460 2.480 166.400 110.800 ;
LAYER met2 ;
RECT 4.240 2.535 166.370 111.510 ;
RECT 4.240 2.535 166.370 111.365 ;
LAYER met3 ;
RECT 5.585 2.555 166.390 109.985 ;
LAYER met4 ;
RECT 33.210 110.120 34.870 111.170 ;
RECT 35.970 110.120 37.630 111.170 ;
RECT 38.730 110.120 40.390 111.170 ;
RECT 41.490 110.120 43.150 111.170 ;
RECT 44.250 110.120 45.910 111.170 ;
RECT 47.010 110.120 48.670 111.170 ;
RECT 49.770 110.120 51.430 111.170 ;
RECT 52.530 110.120 54.190 111.170 ;
RECT 55.290 110.120 56.950 111.170 ;
RECT 58.050 110.120 59.710 111.170 ;
RECT 60.810 110.120 62.470 111.170 ;
RECT 63.570 110.120 65.230 111.170 ;
RECT 66.330 110.120 67.990 111.170 ;
RECT 69.090 110.120 70.750 111.170 ;
RECT 71.850 110.120 73.510 111.170 ;
RECT 74.610 110.120 76.270 111.170 ;
RECT 77.370 110.120 79.030 111.170 ;
RECT 80.130 110.120 81.790 111.170 ;
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RECT 85.650 110.120 87.310 111.170 ;
RECT 88.410 110.120 90.070 111.170 ;
RECT 91.170 110.120 92.830 111.170 ;
RECT 93.930 110.120 95.590 111.170 ;
RECT 96.690 110.120 98.350 111.170 ;
RECT 99.450 110.120 101.110 111.170 ;
RECT 102.210 110.120 103.870 111.170 ;
RECT 104.970 110.120 106.630 111.170 ;
RECT 107.730 110.120 109.390 111.170 ;
RECT 110.490 110.120 112.150 111.170 ;
RECT 113.250 110.120 114.910 111.170 ;
RECT 116.010 110.120 117.670 111.170 ;
RECT 118.770 110.120 120.430 111.170 ;
RECT 121.530 110.120 123.190 111.170 ;
RECT 124.290 110.120 125.950 111.170 ;
RECT 127.050 110.120 128.710 111.170 ;
RECT 129.810 110.120 131.470 111.170 ;
RECT 132.570 110.120 134.230 111.170 ;
RECT 135.330 110.120 136.990 111.170 ;
RECT 138.090 110.120 139.750 111.170 ;
RECT 140.850 110.120 142.510 111.170 ;
RECT 143.610 110.120 145.270 111.170 ;
RECT 146.370 110.120 148.030 111.170 ;
RECT 32.495 109.440 148.745 110.120 ;
RECT 32.495 47.095 42.270 109.440 ;
RECT 44.670 47.095 62.625 109.440 ;
RECT 65.025 47.095 82.980 109.440 ;
RECT 85.380 47.095 103.335 109.440 ;
RECT 105.735 47.095 123.690 109.440 ;
RECT 126.090 47.095 144.045 109.440 ;
RECT 146.445 47.095 148.745 109.440 ;
RECT 6.505 2.555 166.390 111.345 ;
LAYER met4 ;
RECT 19.615 110.120 32.110 111.345 ;
RECT 33.210 110.120 34.870 111.345 ;
RECT 35.970 110.120 37.630 111.345 ;
RECT 38.730 110.120 40.390 111.345 ;
RECT 41.490 110.120 43.150 111.345 ;
RECT 44.250 110.120 45.910 111.345 ;
RECT 47.010 110.120 48.670 111.345 ;
RECT 49.770 110.120 51.430 111.345 ;
RECT 52.530 110.120 54.190 111.345 ;
RECT 55.290 110.120 56.950 111.345 ;
RECT 58.050 110.120 59.710 111.345 ;
RECT 60.810 110.120 62.470 111.345 ;
RECT 63.570 110.120 65.230 111.345 ;
RECT 66.330 110.120 67.990 111.345 ;
RECT 69.090 110.120 70.750 111.345 ;
RECT 71.850 110.120 73.510 111.345 ;
RECT 74.610 110.120 76.270 111.345 ;
RECT 77.370 110.120 79.030 111.345 ;
RECT 80.130 110.120 81.790 111.345 ;
RECT 82.890 110.120 84.550 111.345 ;
RECT 85.650 110.120 87.310 111.345 ;
RECT 88.410 110.120 90.070 111.345 ;
RECT 91.170 110.120 92.830 111.345 ;
RECT 93.930 110.120 95.590 111.345 ;
RECT 96.690 110.120 98.350 111.345 ;
RECT 99.450 110.120 101.110 111.345 ;
RECT 102.210 110.120 103.870 111.345 ;
RECT 104.970 110.120 106.630 111.345 ;
RECT 107.730 110.120 109.390 111.345 ;
RECT 110.490 110.120 112.150 111.345 ;
RECT 113.250 110.120 114.910 111.345 ;
RECT 116.010 110.120 117.670 111.345 ;
RECT 118.770 110.120 120.430 111.345 ;
RECT 121.530 110.120 123.190 111.345 ;
RECT 124.290 110.120 125.950 111.345 ;
RECT 127.050 110.120 128.710 111.345 ;
RECT 129.810 110.120 131.470 111.345 ;
RECT 132.570 110.120 134.230 111.345 ;
RECT 135.330 110.120 136.990 111.345 ;
RECT 138.090 110.120 139.750 111.345 ;
RECT 140.850 110.120 142.510 111.345 ;
RECT 143.610 110.120 145.270 111.345 ;
RECT 146.370 110.120 148.030 111.345 ;
RECT 149.130 110.120 151.505 111.345 ;
RECT 19.615 109.440 151.505 110.120 ;
RECT 19.615 27.375 21.915 109.440 ;
RECT 24.315 27.375 42.270 109.440 ;
RECT 44.670 27.375 62.625 109.440 ;
RECT 65.025 27.375 82.980 109.440 ;
RECT 85.380 27.375 103.335 109.440 ;
RECT 105.735 27.375 123.690 109.440 ;
RECT 126.090 27.375 144.045 109.440 ;
RECT 146.445 27.375 151.505 109.440 ;
END
END tt_um_nickjhay_processor
END LIBRARY
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