Processor

A 32-bit, 5 stage, pipelined processor with full bypassing and exception handling.

This processor is written entirely in structural Verilog.

To use the processor, load a program into instruction memory (imem) and blast it onto an FPGA.

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
.gitignore		.gitignore
Processor.qpf		Processor.qpf
Processor.qsf		Processor.qsf
Processor_assignment_defaults.qdf		Processor_assignment_defaults.qdf
README.md		README.md
SkeletonWaveform.vwf		SkeletonWaveform.vwf
Waveform.vwf		Waveform.vwf
adder4.v		adder4.v
alu.v		alu.v
branchTest.s		branchTest.s
control.v		control.v
counter.v		counter.v
csa32.v		csa32.v
csaBlock4.v		csaBlock4.v
decode_execute.v		decode_execute.v
decoder.v		decoder.v
dflipflop.v		dflipflop.v
dflipflop2.v		dflipflop2.v
dflipflopNeg.v		dflipflopNeg.v
dmem.mif		dmem.mif
dmem.qip		dmem.qip
dmem.v		dmem.v
execute_memory.v		execute_memory.v
fAdder.v		fAdder.v
fetch_decode.v		fetch_decode.v
imem.mif		imem.mif
imem.qip		imem.qip
imem.v		imem.v
insn_signals.v		insn_signals.v
memory_writeback.v		memory_writeback.v
mux32to1.v		mux32to1.v
processor.v		processor.v
processor.v.bak		processor.v.bak
regfile.v		regfile.v
register.v		register.v
register_32.v		register_32.v
rgstr_64.v		rgstr_64.v
shiftLeft1.v		shiftLeft1.v
shiftLeft16.v		shiftLeft16.v
shiftLeft2.v		shiftLeft2.v
shiftLeft4.v		shiftLeft4.v
shiftLeft8.v		shiftLeft8.v
shiftRight1.v		shiftRight1.v
shiftRight16.v		shiftRight16.v
shiftRight2.v		shiftRight2.v
shiftRight4.v		shiftRight4.v
shiftRight8.v		shiftRight8.v
skeleton.v		skeleton.v
skeleton.v.bak		skeleton.v.bak
sx.v		sx.v

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