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Merge remote-tracking branch 'gitlab-plc2/gitlab/asif/arty' into 'rel…
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…ease'.
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@Paebbels
Paebbels committed Sep 9, 2018
2 parents 2dc66ce + 2694cc0 commit 7660a36
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50 changes: 50 additions & 0 deletions ucf/Arty/EthernetPHY.MII.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## Ethernet PHY
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 15
## VCCO: 3.3V (VCC3V3)
## Location: J9
## -----------------------------------------------------------------------------

## single-ended, Clock TX,RX path
## -------------------------------------
## {OUT} CLKIN
set_property PACKAGE_PIN H16 [ get_ports Arty_EthernetPHY_TX_Clock ]
set_property PACKAGE_PIN F15 [ get_ports Arty_EthernetPHY_RX_Clock ]
##
## single-ended, parallel TX path
## -------------------------------------
## {OUT} TXD0
set_property PACKAGE_PIN H14 [ get_ports Arty_EthernetPHY_TX_Data[0] ]
## {OUT} TXD1
set_property PACKAGE_PIN J14 [ get_ports Arty_EthernetPHY_TX_Data[1] ]
## {OUT} TXD2
set_property PACKAGE_PIN J13 [ get_ports Arty_EthernetPHY_TX_Data[2] ]
## {OUT} TXD3
set_property PACKAGE_PIN H17 [ get_ports Arty_EthernetPHY_TX_Data[3] ]
## {OUT} TXEN
set_property PACKAGE_PIN H15 [ get_ports Arty_EthernetPHY_TX_Valid ]
##
##
## single-ended, parallel RX path
## -------------------------------------
## {IN} RXD0
set_property PACKAGE_PIN D18 [ get_ports Arty_EthernetPHY_RX_Data[0] ]
## {IN} RXD1
set_property PACKAGE_PIN E17 [ get_ports Arty_EthernetPHY_RX_Data[1] ]
## {IN} RXD2
set_property PACKAGE_PIN E18 [ get_ports Arty_EthernetPHY_RX_Data[2] ]
## {IN} RXD3
set_property PACKAGE_PIN G17 [ get_ports Arty_EthernetPHY_RX_Data[3] ]
## {IN} RX_DV
set_property PACKAGE_PIN G16 [ get_ports Arty_EthernetPHY_RX_Valid ]
## {IN} RXERR
set_property PACKAGE_PIN C17 [ get_ports Arty_EthernetPHY_RX_Error ]
36 changes: 36 additions & 0 deletions ucf/Arty/EthernetPHY.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## Ethernet PHY
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 15
## VCCO: 3.3V (VCC3V3)
## Location: J9
## -----------------------------------------------------------------------------

## common signals and management
## -------------------------------------
## {OUT}
set_property PACKAGE_PIN C16 [ get_ports EthernetPHY_Reset_n ]
## {OUT}
set_property PACKAGE_PIN G18 [ get_ports EthernetPHY_Reference_Clock ]
## {OUT}
set_property PACKAGE_PIN F16 [ get_ports EthernetPHY_Management_Clock ]
## {OUT}
set_property PACKAGE_PIN G14 [ get_ports EthernetPHY_CRS ]
## {OUT}
set_property PACKAGE_PIN D17 [ get_ports EthernetPHY_COL ]
## {INOUT}
set_property PACKAGE_PIN K13 [ get_ports EthernetPHY_Management_Data ]

# set I/O standard
set_property IOSTANDARD LVCMOS33 [ get_ports -regexp {EthernetPHY_.*} ]
## Ignore timings on async I/O pins
set_false_path -to [ get_ports -regexp {EthernetPHY_.*} ]
set_false_path -from [ get_ports EthernetPHY_Management_Data ]
10 changes: 5 additions & 5 deletions ucf/Arty/GPIO.Button.Special.xdc
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##
## Special Buttons
## -----------------------------------------------------------------------------
## Bank: 35
## VCCO: 3.3V (VCC3V3)
## Bank: 35
## VCCO: 3.3V (VCC3V3)
## Location: BTNR
## -----------------------------------------------------------------------------
## {IN} BTNR; low-active; external 10k pullup resistor
set_property PACKAGE_PIN C2 [ get_ports Arty_GPIO_Button_CPU_Reset ]
set_property PACKAGE_PIN C2 [ get_ports Arty_GPIO_Button_CPU_Reset_n ]
# set I/O standard
set_property IOSTANDARD LVCMOS33 [ get_ports Arty_GPIO_Button_CPU_Reset ]
set_property IOSTANDARD LVCMOS33 [ get_ports Arty_GPIO_Button_CPU_Reset_n ]
# Ignore timings on async I/O pins
set_false_path -from [ get_ports Arty_GPIO_Button_CPU_Reset ]
set_false_path -from [ get_ports Arty_GPIO_Button_CPU_Reset_n ]
23 changes: 23 additions & 0 deletions ucf/Arty/GPIO.Button.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## Button
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 16
## VCCO: VCC3V3
## Location: BTN0,BTN1,BTN2,BTN3
## -----------------------------------------------------------------------------
## {IN} BTN0
set_property PACKAGE_PIN D9 [ get_ports Arty_GPIO_Button[0] ]
## {IN} BTN1
set_property PACKAGE_PIN C9 [ get_ports Arty_GPIO_Button[1] ]
## {IN} BTN2
set_property PACKAGE_PIN B9 [ get_ports Arty_GPIO_Button[2] ]
## {IN} BTN3
set_property PACKAGE_PIN B8 [ get_ports Arty_GPIO_Button[3] ]
4 changes: 2 additions & 2 deletions ucf/Arty/GPIO.LED.RGB.xdc
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##
## LEDs
## -----------------------------------------------------------------------------
## Bank: 35
## VCCO: 3.3V (FPGA_3V3)
## Bank: 35
## VCCO: 3.3V (FPGA_3V3)
## Location: LD0, LD1, LD2, LD3
## -----------------------------------------------------------------------------
## {OUT} LD0.R;
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4 changes: 2 additions & 2 deletions ucf/Arty/GPIO.LED.xdc
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##
## LEDs
## -----------------------------------------------------------------------------
## Bank: 35, 14
## VCCO: 3.3V (FPGA_3V3)
## Bank: 35, 14
## VCCO: 3.3V (FPGA_3V3)
## Location: LD4, LD5, LD6, LD7
## -----------------------------------------------------------------------------
## {OUT} LD4;
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24 changes: 24 additions & 0 deletions ucf/Arty/GPIO.Switch.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## Switch
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 16
## VCCO: VCC3V3
## Location: SW0,SW1,SW2,SW3
## -----------------------------------------------------------------------------

## {IN} SW0
set_property PACKAGE_PIN A8 [ get_ports Arty_GPIO_Switch[0] ]
## {IN} SW1
set_property PACKAGE_PIN C11 [ get_ports Arty_GPIO_Switch[1] ]
## {IN} SW2
set_property PACKAGE_PIN C10 [ get_ports Arty_GPIO_Switch[2] ]
## {IN} SW3
set_property PACKAGE_PIN A10 [ get_ports Arty_GPIO_Switch[3] ]
32 changes: 32 additions & 0 deletions ucf/Arty/PMOD_JA.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## PMOD JA
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 15
## VCCO: 3.3V (VCC3V3)
## Location: JA1,JA2,JA3,JA4,JA7,JA8,JA9,JA10
## -----------------------------------------------------------------------------

## {IN} JA1
set_property PACKAGE_PIN G13 [ get_ports Arty_PMOD_PortA[1] ]
## {IN} JA2
set_property PACKAGE_PIN B11 [ get_ports Arty_PMOD_PortA[2] ]
## {IN} JA3
set_property PACKAGE_PIN A11 [ get_ports Arty_PMOD_PortA[3] ]
## {IN} JA4
set_property PACKAGE_PIN D12 [ get_ports Arty_PMOD_PortA[4] ]
## {IN} JA7
set_property PACKAGE_PIN D13 [ get_ports Arty_PMOD_PortA[7] ]
## {IN} JA8
set_property PACKAGE_PIN B18 [ get_ports Arty_PMOD_PortA[8] ]
## {IN} JA9
set_property PACKAGE_PIN A18 [ get_ports Arty_PMOD_PortA[9] ]
## {IN} JA10
set_property PACKAGE_PIN K16 [ get_ports Arty_PMOD_PortA[10] ]
32 changes: 32 additions & 0 deletions ucf/Arty/PMOD_JB.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## PMOD JB
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 15
## VCCO: 3.3V (VCC3V3)
## Location: JB1_P,JB1_N,JB2_P,JB2_N,JB3_P,JB3_N,JB4_P,JB4_N
## -----------------------------------------------------------------------------

## {IN} JB1_P
set_property PACKAGE_PIN E15 [ get_ports Arty_PMOD_PortB[1]_P ]
## {IN} JB1_N
set_property PACKAGE_PIN E16 [ get_ports Arty_PMOD_PortB[1]_N ]
## {IN} JB2_P
set_property PACKAGE_PIN D15 [ get_ports Arty_PMOD_PortB[2]_P ]
## {IN} JB2_N
set_property PACKAGE_PIN C15 [ get_ports Arty_PMOD_PortB[2]_N ]
## {IN} JB3_P
set_property PACKAGE_PIN J17 [ get_ports Arty_PMOD_PortB[3]_P ]
## {IN} JB3_N
set_property PACKAGE_PIN J18 [ get_ports Arty_PMOD_PortB[3]_N ]
## {IN} JB4_P
set_property PACKAGE_PIN K15 [ get_ports Arty_PMOD_PortB[4]_P ]
## {IN} JB4_N
set_property PACKAGE_PIN J15 [ get_ports Arty_PMOD_PortB[4]_N ]
32 changes: 32 additions & 0 deletions ucf/Arty/PMOD_JC.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## PMOD JC
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 14
## VCCO: 3.3V (VCC3V3)
## Location: JC1_P,JC1_N,JC2_P,JC2_N,JC3_P,JC3_N,JC4_P,JC4_N
## -----------------------------------------------------------------------------

## {IN} JC1_P
set_property PACKAGE_PIN U12 [ get_ports Arty_PMOD_PortC[1]_P ]
## {IN} JC1_N
set_property PACKAGE_PIN V12 [ get_ports Arty_PMOD_PortC[1]_N ]
## {IN} JC2_P
set_property PACKAGE_PIN V10 [ get_ports Arty_PMOD_PortC[2]_P ]
## {IN} JC2_N
set_property PACKAGE_PIN V11 [ get_ports Arty_PMOD_PortC[2]_N ]
## {IN} JC3_P
set_property PACKAGE_PIN U14 [ get_ports Arty_PMOD_PortC[3]_P ]
## {IN} JC3_N
set_property PACKAGE_PIN V14 [ get_ports Arty_PMOD_PortC[3]_N ]
## {IN} JC4_P
set_property PACKAGE_PIN T13 [ get_ports Arty_PMOD_PortC[4]_P ]
## {IN} JC4_N
set_property PACKAGE_PIN U13 [ get_ports Arty_PMOD_PortC[4]_N ]
33 changes: 33 additions & 0 deletions ucf/Arty/PMOD_JD.xdc
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## =============================================================================================================================================================
## Xilinx Design Constraint File (XDC)
## =============================================================================================================================================================
## Board: Digilent - Arty
## FPGA: Xilinx Artix 7
## =============================================================================================================================================================
## General Purpose I/O
## =============================================================================================================================================================
## PMOD JD
## =============================================================================================================================================================
## -----------------------------------------------------------------------------
## Bank: 35
## VCCO: 3.3V (VCC3V3)
## Location: JD1,JD2,JD3,JD4,JD7,JD8,JD9,JD10
## -----------------------------------------------------------------------------

## {IN} JD1
set_property PACKAGE_PIN D4 [ get_ports Arty_PMOD_PortD[1] ]
## {IN} JD2
set_property PACKAGE_PIN D3 [ get_ports Arty_PMOD_PortD[2] ]
## {IN} JD3
set_property PACKAGE_PIN F4 [ get_ports Arty_PMOD_PortD[3] ]
## {IN} JD4
set_property PACKAGE_PIN F3 [ get_ports Arty_PMOD_PortD[4] ]
## {IN} JD7
set_property PACKAGE_PIN E2 [ get_ports Arty_PMOD_PortD[7] ]
## {IN} JD8
set_property PACKAGE_PIN D2 [ get_ports Arty_PMOD_PortD[8] ]
## {IN} JD9
set_property PACKAGE_PIN H2 [ get_ports Arty_PMOD_PortD[9] ]
## {IN} JD10
set_property PACKAGE_PIN G2 [ get_ports Arty_PMOD_PortD[10] ]

2 changes: 1 addition & 1 deletion ucf/Nexys4DDR/EthernetPHY.RMII.xdc
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Expand Up @@ -30,7 +30,7 @@ set_property PACKAGE_PIN D5 [ get_ports Nexys4DDR_EthernetPHY_Clock ]
## {OUT} TXD0
set_property PACKAGE_PIN A10 [ get_ports Nexys4DDR_EthernetPHY_TX_Data[0] ]
## {OUT} TXD1
set_property PACKAGE_PIN A8 [ get_ports Nexys4DDR_EthernetPHY_TX_Data[1] ]]
set_property PACKAGE_PIN A8 [ get_ports Nexys4DDR_EthernetPHY_TX_Data[1] ]
## {OUT} TXEN
set_property PACKAGE_PIN B9 [ get_ports Nexys4DDR_EthernetPHY_TX_Valid ]
##
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