Merge remote-tracking branch 'github-plc2/master' into release

.gitignore

@@ -10,11 +10,11 @@ __pycache__
 
 # ignore build directories
 docs/_build/
-docs/PyInfrastructure/*
-!docs/PyInfrastructure/.gitempty
-!docs/PyInfrastructure/.publish
-!docs/PyInfrastructure/README.md
-!docs/PyInfrastructure/index.rst
+docs/pyIPCMI/*
+!docs/pyIPCMI/.gitempty
+!docs/pyIPCMI/.publish
+!docs/pyIPCMI/README.md
+!docs/pyIPCMI/index.rst
 
 
 # ignore files in netlist/

docs/PoCSphinx.py

@@ -32,9 +32,9 @@
 #
 from sys import path as sys_path
 
-sys_path.append("../py")
+sys_path.append("../lib/pyIPCMI")
 
-from PoC import PileOfCores
+from pyIPCMI import pyIPCMI
 
 # entry point
 parser = PileOfCores(False, False, False, True, sphinx=True).MainParser

docs/QuickStart.rst

@@ -178,7 +178,7 @@ list of steps can be found at :doc:`Integration </UsingPoC/Integration>`.
 
    cd ProjectRoot
    mkdir lib | cd
-   git submodule add https://github.com:VLSI-EDA/PoC.git PoC
+   git submodule add https://github.com/VLSI-EDA/PoC.git PoC
    cd PoC
    git remote rename origin github
    cd ..\..

docs/conf.py

@@ -23,7 +23,8 @@
 # add these directories to sys.path here. If the directory is relative to the
 # documentation root, use os.path.abspath to make it absolute, like shown here.
 sys.path.insert(0, os.path.abspath('.'))
-sys.path.insert(0, os.path.abspath('../py'))
+#sys.path.insert(0, os.path.abspath('../py'))
+sys.path.insert(0, os.path.abspath('../lib/pyIPCMI/'))
 sys.path.insert(0, os.path.abspath('_extensions'))
 sys.path.insert(0, os.path.abspath('_themes/sphinx_rtd_theme'))
 
@@ -62,7 +63,7 @@
 	'autoprogram',               #'sphinxcontrib.autoprogram',
 # local extensions
 	'DocumentMember',
-	'poc'
+	'pyIPCMI'
 ]
 
 for tag in tags:
@@ -82,10 +83,10 @@
 	else:
 		print("Removing old build directory '{0!s}'... [SKIPPED]".format(buildDirectory))
 
-	pyInfrastructureDirectory = Path("PyInfrastructure")
-	print("Removing created files from '{0!s}'...".format(pyInfrastructureDirectory))
-	for path in pyInfrastructureDirectory.iterdir():
-		if (path.name.endswith(".rst") and (path.name != (pyInfrastructureDirectory / "index.rst"))):
+	pyIPCMIDirectory = Path("pyIPCMI")
+	print("Removing created files from '{0!s}'...".format(pyIPCMIDirectory))
+	for path in pyIPCMIDirectory.iterdir():
+		if (path.name.endswith(".rst") and (path.name != (pyIPCMIDirectory / "index.rst"))):
 			print("  {0!s}".format(path))
 			path.unlink()
 	print()
@@ -95,14 +96,14 @@
 
 # Extract Python documentation and generate ReST files.
 autoapi_modules = {
-  'PoC':        {'output': "PyInfrastructure", 'template': "script"},
-  'Base':       {'output': "PyInfrastructure"},
-  'Compiler':   {'output': "PyInfrastructure"},
-  'DataBase':   {'output': "PyInfrastructure"},
-  'Parser':     {'output': "PyInfrastructure"},
-  'Simulator':  {'output': "PyInfrastructure"},
-  'ToolChain':  {'output': "PyInfrastructure"},
-  'lib':        {'output': "PyInfrastructure"}
+  'pyIPCMI':    {'output': "pyIPCMI", 'template': "script"},
+  'pyIPCMI.Base':       {'output': "pyIPCMI"},
+  'pyIPCMI.Compiler':   {'output': "pyIPCMI"},
+  'pyIPCMI.DataBase':   {'output': "pyIPCMI"},
+  'pyIPCMI.Parser':     {'output': "pyIPCMI"},
+  'pyIPCMI.Simulator':  {'output': "pyIPCMI"},
+  'pyIPCMI.ToolChain':  {'output': "pyIPCMI"},
+  'lib':        {'output': "pyIPCMI"}
 }
 
 # Add any paths that contain templates here, relative to this directory.

docs/PyInfrastructure/index.rst → docs/pyIPCMI/index.rst

@@ -4,7 +4,7 @@ Python Infrastructure
 
 .. toctree::
 
-   PoC
+   pyIPCMI
 
 
 .. toctree::
@@ -18,8 +18,8 @@ Python Infrastructure
    lib
 
 .. #
-   automodule:: PoC
+   automodule:: pyIPCMI
    :members:
    :undoc-members:
    :inherited-members:
-   :show-inheritance:
+   :show-inheritance:

src/arith/README.md

@@ -36,14 +36,14 @@ namespace as well as public constants and functions.
  [arith_carrychain_inc]:  arith_carrychain_inc.vhdl
  [arith_convert_bin2bcd]:	arith_convert_bin2bcd.vhdl
  [arith_counter_bcd]:		arith_counter_bcd.vhdl
- [arith_counter_free]:		arith_counter_freev
+ [arith_counter_free]:		arith_counter_free.vhdl
  [arith_counter_gray]:		arith_counter_gray.vhdl
  [arith_counter_ring]:		arith_counter_ring.vhdl
- [arith_div]:				arith_addw.vhdl
+ [arith_div]:				arith_div.vhdl
  [arith_firstone]:			arith_firstone.vhdl
  [arith_muls_wide]:			arith_muls_wide.vhdl
- [arith_prefix_and]:		arith_addw.vhdl
- [arith_prefix_or]:			arith_addw.vhdl
+ [arith_prefix_and]:		arith_prefix_and.vhdl
+ [arith_prefix_or]:			arith_prefix_or.vhdl
  [arith_prng]:				arith_prng.vhdl
  [arith_same]:				arith_same.vhdl
  [arith_scaler]:			arith_scaler.vhdl

src/arith/arith.pkg.vhdl

@@ -121,6 +121,16 @@ package arith is
 			val		: out std_logic_vector(BITS-1 downto 0));
 	end component;
 
+	component arith_trng is
+		generic (
+			BITS : positive	 -- Width: Number of Oscillators
+		);
+		port (
+			clk : in  std_logic;				  							 -- Clock
+			rnd : out std_logic_vector(BITS-1 downto 0)  -- Random Oscillator Samples
+		);
+	end component;
+
 	component arith_muls_wide
 		generic (
 			NA		: integer range 2 to 18;

src/arith/arith_trng.files

@@ -0,0 +1,13 @@
+# EMACS settings: -*-	tab-width: 2; indent-tabs-mode: t -*-
+# vim: tabstop=2:shiftwidth=2:noexpandtab
+# kate: tab-width 2; replace-tabs off; indent-width 2;
+# ==============================================================================
+# Note: all files are relative to PoC root directory
+#
+# Common PoC packages for configuration, synthesis and simulation
+include				"src/common/common.files"
+include				"src/misc/sync/sync_Bits.files"
+
+# PoC.arith
+vhdl		PoC		"src/arith/arith.pkg.vhdl"									# PoC.arith package
+vhdl		PoC		"src/arith/arith_trng.vhdl"									# Top-Level

src/arith/arith_trng.vhdl

@@ -0,0 +1,84 @@
+-- EMACS settings: -*-  tab-width: 2; indent-tabs-mode: t -*-
+-- vim: tabstop=2:shiftwidth=2:noexpandtab
+-- kate: tab-width 2; replace-tabs off; indent-width 2;
+-- =============================================================================
+-- Authors:					Thomas B. Preusser
+--
+-- Entity:					TRNG - True Random Number Generator.
+--
+-- Description:
+-- ------------
+-- This module implements a true random number generator based on sampling
+-- combinational loops of interleaved X(N)OR gates.
+--
+-- Always verify the randomness of this TRNG implementation for your concrete
+-- target platform, for instance, using the dieharder test by Robert G. Brown
+-- [http://www.phy.duke.edu/~rgb/General/dieharder.php], which is also
+-- directly available for many GNU/Linux distributions, e.g. Debian. Ideally,
+-- randomness would be verified for varying operating conditions.
+--
+-- This design involves fast-switching combinational loops on purpose so as
+-- to serve as sources of entropoy. This implies a relevant local power
+-- consumption. Do not cramp large parts of a chip with these TRNGs without
+-- ensuring appropriate heat dissipation. It often requires special
+-- constraints or directives to enforce the proper synthesis of these
+-- combinational loops by the tools.
+--
+-- License:
+-- =============================================================================
+-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
+--										 Chair of VLSI-Design, Diagnostics and Architecture
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--		http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use	IEEE.std_logic_1164.all;
+
+entity arith_trng is
+  generic (
+    BITS : positive  														 -- Width: Number of Oscillators
+	);
+  port (
+    clk : in  std_logic;				  							 -- Clock
+    rnd : out std_logic_vector(BITS-1 downto 0)  -- Random Oscillator Samples
+	);
+end entity;
+
+
+library PoC;
+use PoC.utils.all;
+use PoC.sync.sync_Bits;
+
+architecture rtl of arith_trng is
+  signal osc : std_logic_vector(BITS-1 downto 0) := (others => '-');  -- Oscillators
+  attribute KEEP : boolean;
+  attribute KEEP of osc : signal is true;
+begin
+
+  -- Oscillator Leaves
+  genOscillate : for i in 0 to BITS-1 generate
+	  osc(i) <= ite(i<3, '1', '0') xor osc((i-1)mod BITS) xor osc(i) xor osc((i+1)mod BITS);
+  end generate;
+
+	sync_i : sync_Bits
+		generic map (
+			BITS => BITS
+		)
+		port map (
+			Clock  => clk,
+			Input  => osc,
+			Output => rnd
+		);
+
+end rtl;

src/cache/README.md

@@ -2,4 +2,31 @@
 
 The namespace `PoC.cache` offers different cache implementations, like full-associative, direct-mapped, and set-associative caches.
 
+## Package
+
+The package [`PoC.cache`][cache.pkg] holds all component declarations for this
+namespace as well as public constants and functions.
+
+
+## Entities
+
+ - [`cache_cpu`][cache_cpu]
+ - [`cache_mem`][cache_mem]
+ - [`cache_par`][cache_par]
+ - [`cache_par2`][cache_par2]
+ - [`cache_replacement_policy`][cache_replacement_policy]
+ - [`cache_tagunit_par`][cache_tagunit_par]
+ - [`cache_tagunit_seq`][cache_tagunit_seq]
+
 Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/PoC/cache/index.html).
+
+[cache.pkg]:				cache.pkg.vhdl
+
+[cache_cpu]:				cache_cpu.vhdl
+[cache_mem]:				cache_mem.vhdl
+[cache_par]:				cache_par.vhdl
+[cache_par2]:				cache_par2.vhdl
+[cache_replacement_policy]:				cache_replacement_policy.vhdl
+[cache_tagunit_par]:				cache_tagunit_par.vhdl
+[cache_tagunit_seq]:				cache_tagunit_seq.vhdl
+

src/mem/README.md

@@ -3,6 +3,9 @@
 The namespace `PoC.mem` offers different on-chip and off-chip memory and memory-controller
 implementations.
 
+## Package(s)
+The package [`PoC.mem`][mem.pkg] holds all component declarations for this
+namespace as well as public constants and functions.
 
 ## Sub-Namespace(s)
 
@@ -13,4 +16,6 @@ implementations.
  - [`PoC.mem.ocrom`](ocrom) - On-Chip ROM abstraction layer
  - [`PoC.mem.sdram`](sdram) - SDRAM controllers
 
+[mem.pkg]: mem.pkg.vhdl
+
 Read detailed documentation on [ReadTheDocs](http://poc-library.readthedocs.io/en/latest/IPCores/mem/index.html).

src/misc/README.md

@@ -23,6 +23,7 @@ The package [`PoC.misc`][misc.pkg] holds all component declarations for this nam
 
 ## Entities
 
+ -  [`misc_Delay`][misc_Delay]
  -  [`misc_FrequencyMeasurement`][misc_FrequencyMeasurement] - implements a module to
     measure a signal's frequency relative to a reference clock's frequency.
  -  [`misc_bit_lz`][misc_bit_lz]
@@ -35,5 +36,6 @@ The package [`PoC.misc`][misc.pkg] holds all component declarations for this nam
 
  [misc.pkg]:		misc.pkg.vhdl
 
+ [misc_Delay]: misc_Delay.vhdl
  [misc_FrequencyMeasurement]:	misc_FrequencyMeasurement.vhdl
  [misc_bit_lz]: misc_bit_lz.vhdl

ucf/arith/arith_trng.xdc

@@ -0,0 +1 @@
+set_property -quiet ALLOW_COMBINATORIAL_LOOPS true [get_nets -hierarchical *osc*]