Verilog files issue

[nayiri-k]

I'm trying to use the verilog files generated for the Sky130 SRAMs, but I encounter an error during RTL simulation. It seems the mem signal is used before it is declared (via this declaration: reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];). Moving this declaration before mem is referenced resolved the error in my simulation.

I am assuming that the open-source simulator used to verify the verilog files doesn't treat undeclared signals as an error, so this issue wasn't detected.

[mguthaus]

Thanks, this should be fixed in e6a0093 in the dev branch.

Yes, none of the open-source simulators seem to complain about this, so we didn't catch it. Thanks for pointing it out!