Delay in generated SRAM

[Jianfengusa]

Hi, I am new to SRAM design, and I am using a simple configuration to generate a 128*8 SRAM. Below is the configuration.

I have no issue using OpenRam, but I do have some questions about the generated files.

In the generated Verilog file, there is a parameter "DELAY=3" with the comment "FIXME: This delay is arbitrary".

I would like to know if this delay can be changed to 1, if so under which clock frequency and size of SRAM, and how would the change affect the PNR result from OpenRam.

I really appreciate your help!!

[mguthaus]

Hi,
This is a Verilog simulation delay only and has nothing to do with the actual delay of the SRAM which is available in the .lib file used by P&R. To get accurate delays, you would need to enable characterization but it is very slow. Our analytical models can provide an estimated delay but will be less accurate.

[Jianfengusa]

Hi,

Thank you for the reply.

Since the delay is only for Verilog simulation, then it can be set to 1 for simulation purposes, but this may not represent the correct behaviors of actual SRAM. If I want to simulate the actual behaviors of SRAM I will need to refer to the delay in the .lib file which can be obtained by enabling characterization in OpenRam. Am I understanding you correctly?

[mguthaus]

Usually Verilog isn't used for accurate delay simulation. Instead, you should be relying on the static timing analysis. But, yes, you could add a more realistic delay from the .lib.