Customizing the DELAY and T_HOLD Parameters in Verilog

[ALIASADALI]

Hey!
I have generated the Dual port Sky130 buffer of size 512 bytes and facing the problem of reading data from Port-1 due to time miss-match. I wish to hold the output data for at least 1 to 2 cycles. So I have to change the DELAY and T_HOLD parameters in the Verilog file generated. These things will obviously change the behavior of the GDS generated file. So, could anyone please tell what changing, I have to do in my python script file in macros to customize these DELAY & T_HOLD values.
Thanks

Reference parameters of the Verilog Generated;

parameter DELAY = 100 ; // Original was 3
parameter VERBOSE = 1 ; // Set to 0 to only display warnings
parameter T_HOLD = 0 ; // Original was 1

[mguthaus]

If you want it to hold more than one cycle, you will need to add an external flip flop or latch to your design.

These values are just arbitrary non zero simulation values and don't correspond to an actual delay. Timing estimates are in the .lib file for synthesis but are not very accurate unless you perform simulation characterization which is quite slow and not the default.