Verilog AMS *.vams recognized as Verilog files. #109

VUnit · Feb 15, 2016 · 7a8bb69 · 7a8bb69
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commit 7a8bb69
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diff --git a/vunit/project.py b/vunit/project.py
@@ -815,7 +815,7 @@ def more_recent(file_name, than_file_name):
 
 # lower case representation of supported extensions
 VHDL_EXTENSIONS = (".vhd", ".vhdl")
-VERILOG_EXTENSIONS = (".v", ".vp", ".sv")
+VERILOG_EXTENSIONS = (".v", ".vp", ".sv", ".vams")
 
 
 def file_type_of(file_name):

diff --git a/vunit/test/unit/test_project.py b/vunit/test/unit/test_project.py
@@ -893,6 +893,7 @@ def test_file_type_of(self):
         self.assertEqual(file_type_of("file.vhdl"), "vhdl")
         self.assertEqual(file_type_of("file.sv"), "verilog")
         self.assertEqual(file_type_of("file.v"), "verilog")
+        self.assertEqual(file_type_of("file.vams"), "verilog")
         self.assertRaises(RuntimeError, file_type_of, "file.foo")
 
     def create_dummy_three_file_project(self, update_file1=False):