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Support Verilog-AMS files #109

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cmarqu opened this issue Feb 4, 2016 · 2 comments
Closed

Support Verilog-AMS files #109

cmarqu opened this issue Feb 4, 2016 · 2 comments

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@cmarqu
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cmarqu commented Feb 4, 2016

Verilog-AMS files are often used for modelling analog behaviour because of their wreal port type.
Please add simple support for that.
Initially, this requires accepting *.vams files, and there are ``include "constants.vams"` etc. statements that may not resolve to real files in the filesystem (but https://github.com/VUnit/vunit/blob/master/vunit/parsing/verilog/preprocess.py#L47 fails without a good error message when it's not finding them).

kraigher added a commit that referenced this issue Feb 6, 2016
Making the verilog parser more robust as and provide better error
messages.
kraigher added a commit that referenced this issue Feb 6, 2016
Making the verilog parser more robust as and provide better error
messages.
@LarsAsplund
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@cmarqu @kraigher What's the status on this one? Should it be closed or are there planned extensions to this?

@cmarqu
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cmarqu commented Jun 15, 2016

They are supported now (thanks!), so I'm closing.

@cmarqu cmarqu closed this as completed Jun 15, 2016
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