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Bugfix/axis slave back to back transfers #858

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merged 2 commits into from Aug 31, 2022
Merged

Bugfix/axis slave back to back transfers #858

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f674100
axi_stream_slave: fix memory leak
Aug 21, 2022
fb81a88
axi_stream: fix back-to-back transfer
Aug 21, 2022
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9 changes: 6 additions & 3 deletions vunit/vhdl/verification_components/src/axi_stream_master.vhd
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Expand Up @@ -97,12 +97,15 @@ begin
drive_invalid_output(tdata, tkeep, tstrb, tid, tdest, tuser);
end if;

-- Wait for messages to arrive on the queue, posted by the process above
wait until rising_edge(aclk) and (not is_empty(message_queue) or areset_n = '0');

if (areset_n = '0') then
tvalid <= '0';
wait until areset_n = '1' and rising_edge(aclk);
else
if is_empty(message_queue) then
-- Wait for messages to arrive on the queue, posted by the process above
wait until (not is_empty(message_queue) or areset_n = '0') and rising_edge(aclk);
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All this looks more correct than it was before but I see that the asynchronous reset is basically checked at the rising edge of the clock such that its assertion becomes synchronous rather than asynchronous. Deassertion is correctly synchronous. I think that can be fixed in a separate PR.

end if;

while not is_empty(message_queue) loop
msg := pop(message_queue);
msg_type := message_type(msg);
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6 changes: 5 additions & 1 deletion vunit/vhdl/verification_components/src/axi_stream_slave.vhd
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Expand Up @@ -92,8 +92,10 @@ begin
begin
rnd.InitSeed(rnd'instance_name);
loop
if is_empty(message_queue) then
-- Wait for messages to arrive on the queue, posted by the process above
wait until rising_edge(aclk) and (not is_empty(message_queue));
wait until rising_edge(aclk) and (not is_empty(message_queue));
end if;

while not is_empty(message_queue) loop
msg := pop(message_queue);
Expand Down Expand Up @@ -140,6 +142,8 @@ begin
else
unexpected_msg_type(msg_type);
end if;

delete(msg);
end loop;

notify_bus_process_done <= '1';
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