Agenda for sync meeting 1/8/2021

[tlively]

The next meeting will be Friday, January 8 at 9:00AM - 10:00AM PST/ 6:00PM - 7:00PM CET. Please respond with agenda items you would like to discuss.

If this meeting doesn't already appear on your calendar, or you are a new attendee, please fill out this form to attend.

Agenda so far:

• Q-format multiplication (Saturating Rounding Q-format Multiplication #365) if we get x86-64 benchmarking results for it
• Sign select (Sign Select instructions #124) if @rrwinterton is able to look into its Alder Lake performance
• Expectations about engine optimizations
• Cost tuning methodology LLVM Cost Tuning #404

[omnisip]

If #395 is prototyped on x64/arm64 with the External References mechanism, I'd love to be able to discuss some results in this meeting.

[Maratyszcza]

I'd like to discuss the missing i64x2 instruction forms: PR #381, #411, #412, #414, #415, #417, #418

[lars-t-hansen]

We should revisit the instructions that reached provisional consensus at the last meeting and make sure everyone's on board. (I have no objections to these.)

[Maratyszcza]

Also, lets discuss untyped form of any_true instruction (#416)

[penzn]

We should revisit the instructions that reached provisional consensus at the last meeting and make sure everyone's on board. (I have no objections to these.)

I don't have objections either. Sorry, took me a while to find the issue.

[Maratyszcza]

Sign select (#124) if @rrwinterton is able to look into its Alder Lake performance

I don't have data for Adler Lake, but per Instlatx64 dump Tremont core (Adler Lake predecessor) runs BLENDVPS/BLENDVPD/PBLENDVB with latency of 3 and reciprocal throughput of 2, which is a substantial improvement over Goldmont (latency 4, rcp throughput 4), and is an improvement over the SSE2-level emulation sequence.

[dtig]

As we've had the new proposal freeze for some time now, I'd like to get add a discussion item for Phase 4 timeline/requirements.

[tlively]

Thanks for a productive meeting, everyone! And thanks especially to @dtig and @ngzhian for you help taking the notes.

We had consensus to:

• Merge Load Lane and Store Lane instructions #350 and i64x2.widen_(low/high)_i32x4_(s/u) instructions #290, which were provisionally approved at the last meeting
• Merge Saturating Rounding Q-format Multiplication #365
• Accept the suggestion in any_true instructions should be untyped #416
• Merge i64x2.bitmask instruction #368

There are action items:

• @rrwinterton to look into signselect performance on Alder Lake, using @omnisip's instructions
• @abrown and @penzn to post concerns on i64x2 PRs (i64x2.eq instruction #381, i64x2.ne instruction #411, i64x2.gt_s, i64x2.lt_s, i64x2.ge_s, and i64x2.le_s instructions #412, i64x2.gt_u, i64x2.lt_u, i64x2.ge_u, and i64x2.le_u instructions #414, i64x2.all_true instructions #415, i64x2.min_s and i64x2.max_s instructions #417, i64x2.min_u and i64x2.max_u instructions #418)
• @tlively and @Maratyszcza to get Extended pairwise addition instructions #380 and Prefetch instructions #352 benchmarked.