This repository has been archived by the owner on Dec 22, 2021. It is now read-only.
i64x2.min_u and i64x2.max_u instructions #418
Closed
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
We will probably discuss this in the next meeting, I will like to put down my thoughts ahead of time:
|
|
Code-sequence-wise, these are rather unfortunate on a large number of x86 machines. As with #417, it might make sense to wait on these until more machines have something like |
Maratyszcza
force-pushed
the
minmaxu-64bit
branch
from
1216e30
to
39a2cba
Compare
|
Adding a preliminary vote for the inclusion of i64x2 unsigned min/max operations to the SIMD proposal below. Please vote with - 👍 For including i64x2 unsigned min/max operations |
|
The community group unanimously decided against including these instructions in the 1/29/21 meeting (#429). |
Sign up for free
to subscribe to this conversation on GitHub.
Already have an account?
Sign in.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Introduction
This is proposal to add 64-bit variant of the existing
min_uandmax_uinstructions. Only x86 processors with AVX512 natively support these instructions.Applications
Mapping to Common Instruction Sets
This section illustrates how the new WebAssembly instructions can be lowered on common instruction sets. However, these patterns are provided only for convenience, compliant WebAssembly implementations do not have to follow the same code generation patterns.
x86/x86-64 processors with AVX512F and AVX512VL instruction sets
y = i64x2.min_u(a, b)is lowered toVPMINUQ xmm_y, xmm_a, xmm_by = i64x2.max_u(a, b)is lowered toVPMAXUQ xmm_y, xmm_a, xmm_bx86/x86-64 processors with XOP instruction set
y = i64x2.min_u(a, b)(yis notaandyis notb) is lowered to:VPCOMGTUQ xmm_y, xmm_a, xmm_bVPBLENDVB xmm_y, xmm_b, xmm_a, xmm_yy = i64x2.max_u(a, b)(yis notaandyis notb) is lowered to:VPCOMGTUQ xmm_y, xmm_a, xmm_bVPBLENDVB xmm_y, xmm_a, xmm_b, xmm_yx86/x86-64 processors with AVX instruction set
y = i64x2.min_u(a, b)(yis notaandyis notb) is lowered to:VMOVDQA xmm_tmp, [wasm_i64x2_splat(0x8000000000000000)]VPXOR xmm_y, xmm_tmp, xmm_aVPXOR xmm_tmp, xmm_tmp, xmm_bVPCMPGTQ xmm_y, xmm_y, xmm_tmpVPBLENDVB xmm_y, xmm_a, xmm_b, xmm_yy = i64x2.max_u(a, b)(yis notaandyis notb) is lowered to:VMOVDQA xmm_tmp, [wasm_i64x2_splat(0x8000000000000000)]VPXOR xmm_y, xmm_tmp, xmm_aVPXOR xmm_tmp, xmm_tmp, xmm_bVPCMPGTQ xmm_y, xmm_y, xmm_tmpVPBLENDVB xmm_y, xmm_b, xmm_a, xmm_yx86/x86-64 processors with SSE4.2 instruction set
y = i64x2.min_u(a, b)(yis notaandyis notbanda/b/yis not inxmm0) is lowered to:MOVDQA xmm_y, [wasm_i64x2_splat(0x8000000000000000)]MOVDQA xmm0, xmm_aPXOR xmm0, xmm_yPXOR xmm_y, xmm_bPCMPGTQ xmm0, xmm_yMOVDQA xmm_y, xmm_aPBLENDVB xmm_y, xmm_by = i64x2.max_u(a, b)(yis notaandyis notbanda/b/yis not inxmm0) is lowered to:MOVDQA xmm_y, [wasm_i64x2_splat(0x8000000000000000)]MOVDQA xmm0, xmm_aPXOR xmm0, xmm_yPXOR xmm_y, xmm_bPCMPGTQ xmm0, xmm_yMOVDQA xmm_y, xmm_bPBLENDVB xmm_y, xmm_ax86/x86-64 processors with SSE4.1 instruction set
Based on this answer by user aqrit on Stack Overflow
y = i64x2.min_u(a, b)(yis notaandyis notbanda/b/yis not inxmm0) is lowered to:MOVDQA xmm_y, xmm_bMOVDQA xmm0, xmm_bPSUBQ xmm_y, xmm_aPXOR xmm0, xmm_aPANDN xmm0, xmm_yMOVDQA xmm_y, xmm_bPANDN xmm_y, xmm_aPOR xmm0, xmm_yPSRAD xmm0, 31MOVDQA xmm_y, xmm_aPSHUFD xmm0, xmm0, 0xF5PBLENDVB xmm_y, xmm_by = i64x2.max_u(a, b)(yis notaandyis notbanda/b/yis not inxmm0) is lowered to:MOVDQA xmm_y, xmm_bMOVDQA xmm0, xmm_bPSUBQ xmm_y, xmm_aPXOR xmm0, xmm_aPANDN xmm0, xmm_yMOVDQA xmm_y, xmm_bPANDN xmm_y, xmm_aPOR xmm0, xmm_yPSRAD xmm0, 31MOVDQA xmm_y, xmm_bPSHUFD xmm0, xmm0, 0xF5PBLENDVB xmm_y, xmm_ax86/x86-64 processors with SSE2 instruction set
Based on this answer by user aqrit on Stack Overflow
y = i64x2.min_u(a, b)(yis notaandyis notb) is lowered to:MOVDQA xmm_tmp, xmm_bMOVDQA xmm_y, xmm_bPSUBQ xmm_tmp, xmm_aPXOR xmm_y, xmm_aPANDN xmm_y, xmm_tmpMOVDQA xmm_tmp, xmm_bPANDN xmm_tmp, xmm_aPOR xmm_y, xmm_tmpPSRAD xmm_y, 31MOVDQA xmm_tmp, xmm_bPSHUFD xmm_y, xmm_y, 0xF5PAND xmm_tmp, xmm_yPANDN xmm_y, xmm_aPOR xmm_y, xmm_tmpy = i64x2.max_u(a, b)(yis notaandyis notb) is lowered to:MOVDQA xmm_tmp, xmm_bMOVDQA xmm_y, xmm_bPSUBQ xmm_tmp, xmm_aPXOR xmm_y, xmm_aPANDN xmm_y, xmm_tmpMOVDQA xmm_tmp, xmm_bPANDN xmm_tmp, xmm_aPOR xmm_y, xmm_tmpPSRAD xmm_y, 31MOVDQA xmm_tmp, xmm_aPSHUFD xmm_y, xmm_y, 0xF5PAND xmm_tmp, xmm_yPANDN xmm_y, xmm_bPOR xmm_y, xmm_tmpARM64 processors
y = i64x2.min_u(a, b)(yis notaandyis notb) is lowered to:CMHI Vy.2D, Va.2D, Vb.2DBSL Vy.16B, Vb.16B, Va.16By = i64x2.max_u(a, b)(yis notaandyis notb) is lowered to:CMHI Vy.2D, Va.2D, Vb.2DBSL Vy.16B, Va.16B, Vb.16BARMv7 processors with NEON instruction set
y = i64x2.min_u(a, b)(yis notaandyis notb) is lowered to:VQSUB.U64 Qy, Qa, QbVSUB.I64 Qy, Qa, Qyy = i64x2.max_u(a, b)(yis notaandyis notb) is lowered to:VQSUB.U64 Qy, Qa, QbVADD.I64 Qy, Qb, Qy